Abstract: Bias current generation systems are disclosed. In one embodiment, a bias current generation system comprises a proportional to absolute temperature (PTAT) current source generating a PTAT current, a constant current source generating a constant current, a first current mirror forwarding the PTAT current, a second current mirror forwarding an adjusted current, where the adjusted current is the constant current subtracted by the PTAT current if the constant current subtracted by the PTAT current is greater than zero or the adjusted current is zero if the constant current subtracted by the PTAT current is less than zero, a third current mirror forwarding the adjusted current and a fourth current mirror forwarding a bias current generated by subtracting the PTAT current from the adjusted current.

Abstract: A clock circuit includes a waveform generator, a comparison module, and a clock signal module. The waveform generator is coupled to generate a waveform based on a reference oscillation. The comparison module is coupled to compare the waveform with a plurality of references to produce a plurality of waveform comparisons. The clock signal module is coupled to generate a clock signal from the plurality of waveform comparisons.

Abstract: A drive circuit has a level shift circuit which outputs level-shifted on and off signals each for controlling a power semiconductor element in an on or off state, a first RS flip flop which is supplied with the on signal through a setting input terminal and supplied with the off signal through a resetting input terminal, and which outputs a drive signal to the power semiconductor element, and a logic filter circuit which is provided between the level shift circuit and the first RS flip flop, and which blocks transmission of the on and off signals during the time period from a time at which both the on and off signals become a first logic to a time at which both the on and off signal become a second logic.

Abstract: Circuit and method for a gate control output circuit having reduced voltage stress on the devices is disclosed. In a circuit of MOS transistors for supplying an output to control a transfer gate, the output having a high voltage level that exceeds a supply voltage, first and second clamping circuits are provided. The first clamping circuit ensures a voltage between the gate and the source/drain and drain/source of a PMOS transistor that couples a pumped voltage to the output does not exceed a predetermined voltage. The second clamping circuit ensures that the voltage between the gate of an NMOS transistor and the output which is coupled to the drain/source of the NMOS transistor does not exceed a predetermined amount. The clamping circuits prevent gate stress problems on the transistors by ensuring the voltages between the gates and the source/drain and drain/source terminals do not exceed predetermined voltages.

Abstract: The invention is mainly directed to providing a charge pump circuit which realizes low power consumption. A first clock signal is supplied from an oscillator circuit to capacitor elements forming a charge pump circuit. A current generation circuit controls a current flowing through each of inverters by controlling operation of PMOS and NMOS, and as a result controls the frequency of the first clock signal. A gate and a drain of PMOS are short-circuited, and between the node thereof and a ground terminal a constant current generation circuit and a resistor are connected in parallel. The constant current generation circuit serves to keep the current flowing through the inverters constant against a change of a power supply voltage. Therefore, the frequency of the clock signal is reduced according to the increase of the power supply voltage.

Abstract: The apparatus may include a non-pumping power supply unit configured to generate a supply voltage from a power source voltage and/or configured to output the supply voltage. The apparatus may include a pumping power supply unit and/or a control circuit. The pumping power supply unit may be configured to generate a pump voltage based on the power source voltage and/or configured to output the pump voltage. The control circuit may boost the supply voltage with the pump voltage after a level of the supply voltage reaches the first target voltage level.

Abstract: In a charge pump circuit provided with a positive electric potential generating charge pump circuit that generates a positive electric potential and a negative electric potential generating charge pump circuit that generates a negative electric potential, a parasitic bipolar transistor is prevented from turning on so that the charge pump circuit performs normal voltage boosting operation. First, the negative electric potential generating charge pump circuit is put into operation to generate ?VDD as an output electric potential LV. Since the output electric potential LV is applied to a P-type semiconductor substrate, an electric potential of the P-type semiconductor substrate becomes ?VDD. After that, the positive electric potential generating charge pump circuit is put into operation while the negative electric potential generating charge pump circuit continues its operation.

Abstract: A semiconductor integrated circuit comprising: a first voltage generator configured to generate a first voltage in response to activation of a first enable signal, wherein the first enable signal is generated by detecting a level of the first voltage; and a second voltage generator configured to generate a second voltage in response to activation of at least one of the first enable signal and a second enable signal, wherein the second enable signal is generated by detecting a level of the second voltage.

Abstract: A frequency divider providing an odd integer division factor comprising a binary counter (10) providing an even integer division factor, which is the first even number smaller than the odd division factor, the binary counter having a clock input for receiving a periodical clock signal (Ck) having a frequency. The circuit further comprises an end of count circuit (20) coupled to the binary counter and generating an End Of Count signal (EOC) for a clock (Ck) period after every even integer number periods of the clock signal (Ck), the end of count signal (EOC) being inputted to an input (IN) of the counter (10). The circuit further includes an output generator (30) coupled to the binary counter and to the clock signal (Ck), the output generator (30) generating an output signal (OUT) having a frequency which is substantially equal with the frequency of the frequency signal (Ck) divided by the odd division factor.

Abstract: Since parallel MOSFETs are usually driven with one gate signal in power applications, the current sharing between the MOSFETs is automatically established with regard to the characteristics of the individual MOSFETs. This may lead to a large non-uniformity of the current distribution between the MOSFETs. According to the present invention, an individual control of the on-resistances of the MOSFETs is provided, which allows for an improved current sharing between paralleled MOSFETs.

Abstract: The invention relates to the generation of an electric output signal with a specified frequency and a phase (P) dependent upon a control signal (x) by means of weighted superposition of several input signals (s1, s2, s1*, s2*), which have the specified frequency but different input signals phases, whereby the weighted superposition is applied to a parallel switching of adjustable transconductance stages which are each adjusted by the control signal (x) and to each of which one of the input signals (s1, s2, s1*, s2*) is supplied.

Abstract: The present invention discloses an electronic device and related method for performing a compensation operation on an electronic element, wherein the electronic device includes: a control module, for outputting a control signal according to an input signal; a driver module, coupled to the control module and the electronic element, for providing a driving current to the electronic element according to the control signal; a sensor module, for outputting at least a sensor signal according to a variation of an operation environment; a compensation control module, coupled to the sensor module, for outputting at least a compensation control signal according to the at least a sensor signal and the input signal; and a compensation driver module, coupled to the electronic element and the compensation control module, for providing at least a compensation driving current to the electronic element according to the at least a compensation control signal.

Abstract: A voltage generating apparatus including a current source, a first voltage source, a second voltage source, a first differential pair, a second differential pair, a voltage divider and a current mirror is provided. The voltage divider is used for reducing a voltage with a negative temperature coefficient, so as to reduce the amplification ratio of the voltage with a positive temperature coefficient used for compensating the negative temperature coefficient.

Abstract: A charge pump system is provided that includes at least one first pump for generating a first working voltage, a second pump for generating a second working voltage, and a third pump for generating a third working voltage. The first pump is connected to an internal supply voltage reference that can having a limited value, and has an output terminal connected to the second and third pumps so as to supplying them with the first working voltage as their supply voltage. A method is also provided for managing the generation of voltages to be used with such a charge pump system.

Abstract: An active voltage-clamping gate driving circuit comprises a difference comparison circuit for receiving a reference voltage, a gate driving signal, and a preset voltage level, and outputting a voltage comparison signal; and a gate driving circuit for receiving an input signal and the voltage comparison signal, and outputting a gate driving signal. The voltage comparison signal controls the gate driving circuit. When a level difference between the gate control signal and the reference voltage is equal to the preset voltage level, the gate driving circuit is turned off, so that the level of the gate control signal is clamped to the preset voltage level, and the gate driving circuit does not output quiescent direct current under the clamped state.

Abstract: A power supply management device including a current limiting protection circuit. The power supply management device may include an output terminal, a first transistor, a replication circuit, a comparator circuit, and a control circuit. The first transistor may provide an output current to the output terminal of the power supply management device. The replication circuit may be connected to the first transistor and may replicate the output current to a separate path to monitor the output current. The comparator circuit may be connected to the replication circuit and may compare the replicated output current to a current reference. The control circuit may be connected to the first transistor and to the comparator circuit. In response to the replicated output current being greater than the current reference, the control circuit may limit the output current the first transistor provides to the output terminal to an amount corresponding to the current reference.

Abstract: A fuse-fetching circuit comprises a plurality of fuses, a plurality of first switches and a shift register. Each of the first switches includes a first data end, a second data end and a control end. The first data end is connected to the fuse, and the control end is controlled by a fuse-fetching signal. The shift register includes a plurality of registers, each of which includes a first latch, a first transmission gate, a second latch and a second transmission gate. The first latch is connected to the second data end of the first switch.

Abstract: A voltage converting circuit and a battery device, aimed at the problem that the breakdown voltage required for the driving input of the selected switch element is increased as the potential of the selected power storage device is increased when a power storage device is selected from a plurality of power storage devices that are connected in series. A certain drive voltage for turning on p-type MOS transistors Q3, Q4 of selection circuit 121 is generated based on a certain drive current Ion flowing from one power storage element to ground level GND. In other words, even if the power storage device selected by selection circuit 121 has a high potential with respect to ground level GND, the drive voltage applied between the gate and source of MOS transistors Q3, Q4 can be held substantially constant.

Abstract: Provided is a voltage level shift circuit including: a first voltage level shift circuit formed of a P-channel enhancement type transistor (M1) and an N-channel depletion type MOS transistor (M3); and a second voltage level shift circuit formed of a P-channel enhancement type transistor (M2) and an N-channel depletion type MOS transistor (M4). In the voltage lever shift circuit, a cascode circuit using an N-channel depletion type transistor (M5) is serially connected to the first voltage level shift circuit, a cascode circuit using an N-channel depletion type transistor (M6) is serially connected to the second voltage level shift circuit, and a unit for complementarily controlling bias voltages of the respective cascode circuits. As a result, an output signal of the voltage level shift circuit connected to an input of a differential amplifier circuit, for expanding an input voltage range of a signal, is not affected by fluctuations in power supply voltage.

Abstract: A reference voltage device and a reference voltage generating method thereof. The reference voltage device comprises a bandgap unit, a voltage generating unit, a comparator, and a calibration controller. The calibration controller controls the voltage generating unit to generate a final calibrating voltage to serve as an ideal target voltage. The bandgap unit generates a bandgap voltage with zero offset voltage according to the final calibrating voltage to serve as a reference voltage. The variation of the reference voltage output by the reference voltage device is thus reduced.