Abstract: In one aspect, an apparatus includes a ready circuit to output a ready indicator when a supply voltage provided to the ready circuit and a voltage regulator is sufficient to operate the voltage regulator. In turn, the voltage regulator is to receive the supply voltage and output a regulated voltage, receive a first current from the ready circuit and control the regulated voltage based on the first current when the ready indicator is inactive. The apparatus further includes a bias circuit to receive the regulated voltage and generate one or more bias currents, which may be provided to an output circuit to output one or more bias outputs to one or more client circuits therefrom.

Abstract: An charge pump architecture capable of generating ultra high DC voltages but implemented in low voltage CMOS technology uses a cascade of NMOS stages with the bulk terminal of the latter stages biased to a voltage just below the reverse breakdown of the parasitic bulk diode. The bias voltage is tapped from a lower voltage point within the charge pump. The upper limit of the output voltage is then increased to the maximum allowable oxide voltage plus the parasitic diode reverse bias breakdown voltage.

Abstract: A reference voltage generating circuit with extremely low temperature dependence is provided. The reference voltage generating circuit includes a BGR circuit which generates a bandgap reference voltage; a bandgap current generating circuit which generates a bandgap current according to the bandgap reference voltage; a PTAT current generating circuit which generates a current proportional to the absolute temperature; and a linear approximate correction current generating circuit which compares the current generated by the PTAT current generating circuit and the bandgap current to generate a correction current, and the BGR circuit adds, to the bandgap reference voltage, a correction voltage generated based on the correction current.

Abstract: A current generating circuit, which comprises: a first capacitor, comprising a first terminal and a second terminal; a second capacitor, comprising a first terminal and a second terminal; a first charge adjusting path, arranged for adjusting charges of the first capacitor according to a first charge adjusting voltage; a second charge adjusting path, arranged for adjusting charges of the second capacitor according to the first charge adjusting voltage; and a current generating path, coupled to the first capacitor and the second capacitor, arranged for generating a target current based on a difference between a first voltage provided by the first capacitor and a second voltage provided by the second capacitor.

Abstract: Disclosed is a semiconductor device that includes an N-channel MOS transistor and a control voltage generation circuit. The N-channel MOS transistor controls the supply of a power supply voltage obtained by stepping down a DC voltage. The control voltage generation circuit clips the gate voltage of the N-channel MOS transistor at a control voltage not higher than a predetermined voltage in accordance with the DC voltage.

Abstract: A circuit comprises a plurality of electronic components integrated on a substrate, and a trim arrangement arranged to provide trim data to a respective electronic component of the plurality of electronic components. The electronic components are programmable such that the electronic components are enabled to be assigned desired properties. The trim arrangement comprises a first trim data source providing a first trim data set represented by a first number of bits, and at least one second trim data source providing a second trim data set representing an offset from the first trim data set. The second trim data set is represented by a second number of bits. The second number is less than the first number. At least one of the plurality of electronic components is provided with a trim data set formed from the first and second trim data sets such that the at least one of the plurality of electronic components is enabled to adjust its properties based on the trim data set.

Abstract: Circuits for programming an electrical fuse, methods for programming an electrical fuse, and methods for designing a silicon-controlled rectifier for use in programming an electrical fuse. A programming current for the electrical fuse is directed through the electrical fuse and the silicon-controlled rectifier. Upon reaching a programmed resistance value for the electrical fuse, the silicon-controlled rectifier switches from a low-impedance state to a high-impedance state that interrupts the programming current.

Abstract: A calibration circuit of a semiconductor apparatus may include: a reference voltage generator suitable for generating first and second pull-up reference voltages based on a pull-up control signal, and generating first and second pull-down reference voltages based on a pull-down control signal; and a calibrator suitable for generating a pull-up resistor code corresponding to an external reference resistor based on the first and second pull-up reference voltages, and generating a pull-down resistor code corresponding to the external reference resistor based on the first and second pull-down reference voltages and the pull-up resistor code.

Abstract: A system-in-package includes first and second semiconductor chips disposed in a first region over a substrate, and a controller disposed in a second region over the substrate and selectively supplying a power supply voltage to the first or second semiconductor chip based on a data output operation of the first and second semiconductor chips, wherein each of the first and second semiconductor chips includes a first power supply region coupled with the controller through a first line and receiving the power supply voltage from the controller in common during an input/output operation of the first and second semiconductor chips, an output driver suitable for outputting data, and a second power supply region independently coupled with the controller through one of a second line and a third line and independently receiving the power supply voltage for an operation of the output driver from the controller during the data output operation.

Abstract: A processing system for an input device includes a receiver module and a charge distributor. The receiver module includes a first charge integrator coupled to a first sensor electrode and configured to integrate a charge on the first sensor electrode. The charge distributor includes a current conveyor and a plurality of output stages coupled to the current conveyor, wherein a first output stage of the plurality of output stages comprises a plurality of current mirrors and is configured to output a first scaled mirrored charge to offset the charge integrated by the first charge integrator, wherein the first scaled mirrored charge is based on a charge signal provided via the current conveyor.

Abstract: Physical layouts of ratioed circuit elements, such as transistors, are disclosed. Such layouts can maintain electrical characteristics of the ratioed circuit elements relative to one another in the presence of mechanical stresses applied to an integrated circuit, such as an integrated circuit encapsulated in plastic. The ratioed circuit elements can include first and second composite circuit elements formed of first and second groups of circuit elements, respectively, arranged around a center point. The first group of circuit elements can be arranged on a grid and the second group of circuit elements can include four circuit elements spaced approximately the same distance from the center point. Each of the circuit elements in the second group can be off the grid in at least one dimension. The first and second groups of circuit elements can be arranged around a perimeter of dummy circuit elements in some embodiments.

Abstract: A charge pump circuit includes a delay circuit, a transistor, and a capacitor. The charge pump receives an input signal and outputs an output signal. The delay circuit receives a first signal based on the input signal and outputs a first delayed signal. The transistor includes a gate, a first channel node, and a second channel node. The first channel node receives the first signal. The second channel node is connected to the output and to a first plate of the capacitor. A second plate of the capacitor receives a second signal based on the first delayed signal. The charge pump circuit is adapted to operate such that the voltage range of the output signal is greater than the voltage range of the input signal.

Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.

Abstract: A supply voltage regulation system for an IC including a temperature sensor that detects temperature of the IC, a scaling resistor coupled between a power grid and a feedback node of the IC, a regulator amplifier that compares a voltage of the feedback node with a reference voltage for developing a supply voltage for the IC, and a temperature scaling circuit that drives a scaling current to the scaling resistor via the feedback node to adjust the supply voltage based on temperature. The temperature scaling circuit may include one or more comparators that compare a temperature signal with corresponding temperature thresholds for selectively applying one or more bias currents to the scaling resistor. The scaling resistor may be coupled to a hot point of the power grid. A voltage difference between a hot point of a ground grid may be converted to a bias current applied to the scaling resistor.

Abstract: In one integrated circuit embodiment, a programmable pull-down output buffer is calibrated by sequentially configuring the buffer at different drive-strength levels and adjusting a source current applied to the buffer until the voltage at an input node of the buffer reaches a reference voltage level. A programmable pull-up output buffer is then calibrated by sequentially configuring a pull-down output buffer based on the pull-down buffer calibration results and adjusting the drive-strength level of the pull-up buffer until the voltage at a common node between the two buffers reaches a reference voltage level. Average calibration results are generated by averaging multiple calibration results for each setting. Output buffers are thereby calibrated to compensate for PVT variations without using any external resistors and without requiring any I/O pins of the integrated circuit.

Abstract: In an embodiment, an apparatus includes: a plurality of islands configured on a semiconductor die, each of the plurality of islands having a plurality of cores; and a plurality of network switches configured on the semiconductor die and each associated with one of the plurality of islands, where each network switch includes a plurality of output ports, a first set of the output ports are each to couple to the associated network switch of an island via a point-to-point interconnect and a second set of the output ports are each to couple to the associated network switches of a plurality of islands via a point-to-multipoint interconnect. Other embodiments are described and claimed.

Abstract: In accordance with an embodiment, a temperature sensor includes a proportional to absolute temperature (PTAT) current generator having a first current output configured to provide a first temperature dependent current, a first curvature compensation circuit configured to provide a first compensating current to an internal node of the PTAT current generator, and a second curvature compensation circuit configured to add a second compensating current to the first current output. The first compensating current has a first non-linearity with respect to temperature, a portion of the first non-linearity is present in the first temperature dependent current, the second compensating current includes a second non-linearity with respect to temperature, such that the second non-linearity in the second compensating current substantially cancels out the first non-linearity in the first temperature dependent current.

Abstract: A wireless power distribution system and method for power tools and other battery-powered devices. The system includes a power transmitter and a plurality of power harvesters or receivers. The receivers are located in power tools, battery packs that are attachable to and detachable from the power tools, a device or case that is interfaceable with the power tool or battery pack, conventionally-sized batteries, or other battery-powered devices. The power transmitter transmits radio frequency (“RF”) power signals to the receivers that are within transmission range of the power transmitter. The receivers receive the RF power signals and convert the RF power signals into direct current. The direct current is used to charge a battery, directly power a tool, etc.

Abstract: A passive filter for connection between an AC source and a load, in either three-phases or in a single-phase arrangement. The filter includes, for each phase, a trap circuit having an inductor in series with a capacitor, the trap circuit having at least two terminals. A line reactor is connected between the AC source and the load, the line reactor having at least an input terminal, an output terminal and a tap terminal. A switch selectively connects at least one of the trap circuit terminals to a selected one of the line reactor terminals. The switch is capable of selecting which of the trap circuit terminals to connect to which of the line reactor terminals on the basis of a level of voltage distortion being experienced by the AC source, or on the basis of a calculated level of background voltage total harmonic distortion.

Abstract: There is provided a reference voltage generating apparatus including: a reference voltage source, a voltage retaining circuit, a switch and a controller. The reference voltage source generates a reference voltage. The voltage retaining circuit includes a first element circuit and a second element circuit, and the voltage retaining circuit outputs a voltage of a connection node between a first terminal of the first element circuit and a second terminal of the second element circuit. The switch is connected between the connection node and the reference voltage source. The controller controls the reference voltage source and the switch. The first element circuit includes at least a resistance component and the first element circuit is supplied with a first voltage at a third terminal and the second element circuit includes a resistance component and a capacity component and the second element circuit is supplied with a second voltage at a fourth terminal.