Abstract: A method for manufacturing a semiconductor structure includes forming a fin over a substrate, wherein the fin includes first semiconductor layers and second semiconductor layers alternating stacked. The method also includes forming an isolation feature around the fin, forming a dielectric feature over the isolation feature, forming a cap layer over the fin and the dielectric feature, oxidizing the cap layer to form an oxidized cap layer, forming source/drain features passing through the cap layer and in the fin, removing the second semiconductor layers in the fin to form nanostructures, and forming a gate structure wrapping around the nanostructures.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a plurality of nanostructures vertically stacked and separated from one another. The semiconductor structure also includes a gate stack wrapping around the plurality of nanostructures. The semiconductor structure also includes a source/drain feature adjacent to the plurality of nanostructures. The semiconductor structure also includes a semiconductor inner spacer layer interposing between the gate stack and the source/drain feature and interposing between the plurality of nanostructures and the source/drain feature.

Abstract: A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.

Abstract: Integrated circuit transistor structures and processes are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent channel regions during fabrication. The n-MOS transistor device may include at least 70% germanium (Ge) by atomic percentage. In an example embodiment, source and drain regions of the transistor are formed using a low temperature, non-selective deposition process of n-type doped material. In some embodiments, the low temperature deposition process is performed in the range of 450 to 600 degrees C. The resulting structure includes a layer of doped mono-crystyalline silicon (Si), or silicon germanium (SiGe), on the source/drain regions. The structure also includes a layer of doped amorphous Si:P (or SiGe:P) on the surfaces of a shallow trench isolation (STI) region and the surfaces of contact trench sidewalls.

Abstract: A semiconductor device includes a first device disposed in an NMOS region of the semiconductor device. The first device includes a first gate-all-around (GAA) device having a vertical stack of nano-structure channels. The semiconductor device also includes a second device in a PMOS region of the semiconductor device. The second device includes a FinFET that includes a fin structure having a fin width. The fin structure is separated from an adjacent fin structure by a fin pitch. A maximum channel width of the nano-structure channels is no greater than a sum of: the fin width and the fin pitch. Alternatively, the second device includes a second GAA device having a different number of nano-structure channels than the first GAA device.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned contacts and methods of manufacture. The structure includes: adjacent diffusion regions located within a substrate material; sidewall structures above an upper surface of the substrate material, aligned on sides of the adjacent diffusion regions; and a contact between the sidewall structures and extending to within the substrate material between and in electrical contact with the adjacent diffusion regions.

Abstract: A manufacturing method of semiconductor device includes providing a substrate, forming a sacrificial layer on the substrate, forming a resin layer on the sacrificial layer, disposing first chips on the sacrificial layer, and forming a first dielectric layer having trenches and surrounding the first chips, wherein an upper surface of the first dielectric layer and an upper surface of the resin layer are at a same plane.

Abstract: A semiconductor device includes a substrate having a first surface and a second surface opposite to each other, and having an active region located on the first surface and defined by a first isolation region; a plurality of active fins arranged on the active region, extending in a first direction, and defined by a second isolation region having a second depth smaller than a first depth of the first isolation region; a buried conductive wiring in a trench adjacent to the plurality of active fins, and extending in a direction of the trench; a filling insulation portion in the trench, and having the buried conductive wiring therein; an interlayer insulation layer on the first and second isolation regions and on the buried conductive wiring; a contact structure penetrating the interlayer insulation layer, and contacting the buried conductive wiring; and a conductive through structure extending through the substrate from the second surface to the trench, and contacting the buried conductive wiring.

Abstract: A technique relates to a semiconductor device. A source/drain layer is formed. Fins with gate stacks are formed in a fill material, a dummy fin template including at least one fin of the fins and at least one gate stack of the gate stacks, the fins being formed on the source/drain layer. A trench is formed through the fill material by removing the dummy fin template, such that a portion of the source/drain layer is exposed in the trench. A source/drain metal contact is formed on the portion of the source/drain layer in the trench.

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate, the gate structure being surrounded by a first interlayer dielectric (ILD) layer; forming a trench in the first ILD layer adjacent to the fin; filling the trench with a first dummy material; forming a second ILD layer over the first ILD layer and the first dummy material; forming an opening in the first ILD layer and the second ILD layer, the opening exposing a sidewall of the first dummy material; lining sidewalls of the opening with a second dummy material; after the lining, forming a conductive material in the opening; after forming the conductive material, removing the first and the second dummy materials from the trench and the opening, respectively; and after the removing, sealing the opening and the trench by forming a dielectric layer over the second ILD layer.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.

Abstract: A display device includes an optical filter substrate including: a substrate; a first color filter on the substrate; a second color filter on the substrate, the second color filter spaced apart from the first color filter; a first color conversion element on the first color filter, the first color conversion element converting incident light into light of a first color; a second color conversion element on the second color filter, the second color conversion element converting the incident light into light of a second color; and a black matrix located between the first color conversion element and the second color conversion element, and between the first color filter and the second color filter.

Abstract: Disclosed is a display device including: a substrate; a first insulating film over the substrate, the first insulating film exposing a part of the substrate to provide an exposed surface to the substrate; a second insulating film in contact with the exposed surface and a first side surface of the first insulating film; and a first wiring over the second insulating film and in contact with the exposed surface, the first insulating film, and the second insulating film. The display device may further possess a third insulating film spaced from the second insulating film and in contact with the exposed surface. The first insulating film has a second side surface opposing the first side surface through the exposed surface. The third insulating film may be in contact with the second side surface, and the wiring may be located over and in contact with the third insulating film.

Abstract: The present invention provides an organic light-emitting diode (OLED) display panel including a substrate, a thin-film transistor, an insulating layer, an auxiliary electrode, an organic light-emitting layer, a shielding stage, and a common electrode. The common electrode is electrically connected to the auxiliary electrode. The shielding stage includes at least one organic material layer. An angle between the shielding stage and the substrate is a threshold value.

Abstract: A high voltage semiconductor device includes a semiconductor substrate, first and second deep well regions, and first and second well regions disposed in the semiconductor substrate. The second deep well region is located above the first deep well region. The first well region is located above the first deep well region. The second well region is located above the second deep well region. A conductivity type of the second deep well region is complementary to that of the first deep well region. A conductivity type of the second well region is complementary to that of the first well region and the second deep well region. A length of the second deep well region is greater than or equal to that of the second well region and less than that of the first deep well region. The first well region is connected with the first deep well region.

Abstract: A first wiring line and a second wiring line are extended to an upper face of a resin substrate exposed from a slit formed in at least one layer of an inorganic insulating film, a first flattening film is provided within the slit which exposes the upper face of the resin substrate between the portions to which the first wiring line and the second wiring line are extended, and the first wiring line and the second wiring line are electrically connected to each other via a third wiring line provided between an end face of the first flattening film and the upper face of the resin substrate.

Abstract: A fin field effect transistor (FinFET) includes a drain region, a merged drift region, and a plurality of fins. The drain region extends above a surface of a semiconductor substrate and has a first dopant concentration of first conductivity type. The merged drift region extends above the substrate surface and touches the drain region, and has a second lower dopant concentration of the first conductivity type. The plurality of fins extend above the substrate surface and each fin is directly connected to the merged drift region. Each fin is connected to a source region having the first conductivity type at a distal end of that fin from the merged drift region.

Abstract: An integrated circuit structure includes a first well, a second well, a third well, a first set of implants and a second set of implants. The first well includes a first dopant type, a first portion extending in a first direction and having a first width, and a second portion adjacent to the first portion of the first well, extending in the first direction and having a second width. The second well has a second dopant type and is adjacent to the first well. The third well has the second dopant type, and is adjacent to the first well. The first portion of the first well is between the second well and the third well. The first set of implants is in the first portion of the first well, the second well and the third well. The second set of implants is in the second portion of the first well.

Abstract: A vertical metal oxide semiconductor field effect transistor (MOSFET) and a method for forming a vertical MOSFET is presented. The MOSFET comprises: a top contact; a bottom contact; a nanowire (602) forming a charge transport channel between the top contact and the bottom contact; and a wrap-around gate (650) enclosing the nanowire (602) circumference, the wrap-around gate (650) having an extension spanning over a portion of the nanowire (602) in a longitudinal direction of the nanowire (602), wherein the wrap-around gate (650) comprises a gate portion (614) and a field plate portion (616) for controlling a charge transport in the charge transport channel, and wherein the field plate portion (616) is arranged at a first radial distance (636) from the center of the nanowire (602) and the gate portion (614) is arranged at a second radial distance (634) from the center of the nanowire (602); characterized in that the first radial distance (636) is larger than the second radial distance (634).

Abstract: To provide a semiconductor device, an image pickup device, and a method for manufacturing the semiconductor device that reduce wiring capacity by using gaps and maintain mechanical strength and reliability. A semiconductor device including: a multilayered wiring layer in which insulating layers and diffusion preventing layers are alternately laminated and a wiring layer is provided inside; a through-hole that is provided to penetrate through at least one or more insulating layers from one surface of the multilayered wiring layer and has an inside covered with a protective side wall; and a gap that is provided in at least one or more insulating layers immediately below the through-hole.