Patents Examined by Jeremy J Joy
  • Patent number: 10529590
    Abstract: The present disclosure provides an annealing method for improving interface bonding strength of a wafer. The method includes: providing a substrate, the substrate having a bonding interface; performing a first annealing step, wherein the first annealing step is practiced in an oxygen-containing atmosphere, and an oxidation protection layer is formed on a surface of the substrate through the annealing step; and performing a second annealing step upon the first annealing step, wherein a temperature of the second annealing step is higher than that of the first annealing step, and the second annealing step is practiced in a nitrogen-free environment.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: January 7, 2020
    Assignee: Shanghai Simgui Technology Co., Ltd.
    Inventors: Xing Wei, Yongwei Chang, Meng Chen, Guoxing Chen, Lu Fei, Xi Wang
  • Patent number: 10529879
    Abstract: A photoelectric conversion device may include a substrate, a photoactive layer disposed on the substrate, and a first electrode and a second electrode respectively connected to corresponding edges of the photoactive layer. The photoactive layer may include a first oxide semiconductor layer on the substrate, and a plurality of quantum dot layers and a plurality of second oxide semiconductor layers that are alternately formed on the first oxide semiconductor layer.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: January 7, 2020
    Assignees: SAMSUNG ELECTRONICS CO., LTD., CHEONGJU University Industry & Academy Cooperation Foundation
    Inventors: Kyungsang Cho, Sangyeol Lee, Chanwook Baik
  • Patent number: 10497731
    Abstract: A photoelectric conversion device includes a semiconductor substrate having a photoelectric conversion unit, a magnetic layer arranged over an opposite side to a light-receiving face of the semiconductor substrate, and an infrared ray absorbing layer arranged between the semiconductor substrate and the magnetic layer.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: December 3, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yuichi Kazue, Takahiro Hachisu
  • Patent number: 10483170
    Abstract: A method includes providing a substrate including a first fin element and a second fin element extending from the substrate. A first layer including an amorphous material is formed over the first and second fin elements, where the first layer includes a gap disposed between the first and second fin elements. An anneal process is performed to remove the gap in the first layer. The amorphous material of the first layer remains amorphous during the performing of the anneal process.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: November 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: De-Wei Yu, Chia Ping Lo, Liang-Gi Yao, Weng Chang, Yee-Chia Yeo, Ziwei Fang
  • Patent number: 10461063
    Abstract: A light-emitting device according to an embodiment includes a light-emitting part and an external wiring. The light-emitting part includes: a pair of insulating substrates that has light transmissive property and flexibility; a plurality of light-emitting elements arranged between the pair of insulating substrates; an internal wiring pattern that is provided between the pair of insulating substrates, and is connected to the light-emitting elements; and a resin layer that has light transmissive property and insulating property, and is provided between the pair of insulating substrates. An end of the external wiring is divided into a plurality of wirings having a line width that is narrower than a line width of the internal wiring pattern. An end of the internal wiring pattern is bonded, at an end of the insulating substrates, to the end of the external wiring that is divided into a plurality of wirings by an anisotropic conductive adhesive.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: October 29, 2019
    Assignee: Toshiba Hokuto Electronics Corporation
    Inventor: Keiichi Maki
  • Patent number: 10461173
    Abstract: A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor (vFET) including top and bottom source/drain regions produced in one epitaxial growth process. The vFET may contain a semiconductor substrate; a fin above the semiconductor substrate; a structure on a middle portion of each sidewall of the fin, wherein a lower portion of each sidewall of the fin adjacent the semiconductor substrate and at least a top of the fin are uncovered by the structure; a top source/drain (S/D) region on at least the top of the fin; and a bottom S/D region on the lower portion of the fin and the semiconductor substrate. The structure on each sidewall may be a gate or a dummy gate, i.e., the vFET may be formed in a gate-first or a gate-last process.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: October 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ajey Poovannummoottil Jacob, Xuan Anh Tran, Hui Zang, Bala Haran, Suryanarayana Kalaga
  • Patent number: 10461037
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first overlay grating over a substrate. The first overlay grating has a first strip portion and a second strip portion. The method includes forming a first layer over the first overlay grating. The first layer has a first trench elongated in a second elongated axis, the second elongated axis is substantially perpendicular to the first elongated axis, and the first trench extends across the first strip portion and the second strip portion. The method includes forming a second overlay grating over the first layer. The second overlay grating has a third strip portion and a fourth strip portion. The third strip portion and the fourth strip portion are elongated in the first elongated axis and are spaced apart from each other.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: October 29, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Long-Yi Chen, Jia-Hong Chu, Chi-Wen Lai, Chia-Ching Liang, Kai-Hsiung Chen, Yu-Ching Wang, Po-Chung Cheng, Hsin-Chin Lin, Meng-Wei Chen, Kuei-Shun Chen
  • Patent number: 10460971
    Abstract: Methods of bonding chips to a substrate and transfer wafers used for such bonding include bonding chips to a first support wafer by a first adhesive layer. The chips are bonded to a second support wafer by a second adhesive layer. Regions of the first adhesive layer are selectively weakened to decrease an adhesive strength in weakened regions. The weakened regions correspond to a subset of chips. The second support wafer is separated from the first wafer, such that the subset of chips in the weakened regions debond from the first support wafer. The subset of chips are bonded to a target substrate.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: October 29, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Akihiro Horibe
  • Patent number: 10461040
    Abstract: Capacitor devices having multiple capacitors with similar nominal capacitances are described. The capacitors may be multilayer ceramic capacitors (MLCCs) and may be fabricated employing class 2 materials. The arrangement of the electrodes in the device may reduce relative variations between the capacitors of the device. The capacitor devices may be allow high performance and compact electrical circuits that may employ matched capacitors.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: October 29, 2019
    Assignee: APPLE INC.
    Inventors: Paul A. Martinez, Ming Y. Tsai, Won Seop Choi
  • Patent number: 10461117
    Abstract: A method for manufacturing a semiconductor structure includes the following steps. A first carrier is adhered to a first surface of a wafer by a first temporary bonding layer. A second surface of the wafer facing away from the first carrier is etched to form at least one through hole and at least one trench, in which a conductive pad of the wafer is exposed through the through hole. An isolation layer is formed on the second surface of the wafer, a sidewall of the through hole, and a sidewall of the trench. A second carrier is adhered to the second surface of the wafer by a second temporary bonding layer, and thus the through hole and the trench are covered by the second carrier. The first carrier and the first temporary bonding layer are removed.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: October 29, 2019
    Assignee: XINTEC INC.
    Inventors: Yen-Shih Ho, Tsang-Yu Liu, Chia-Sheng Lin, Chaung-Lin Lai
  • Patent number: 10446725
    Abstract: A light emitting device includes a mounting board, first and second light emitting elements and a light reflective covering member. The mounting board includes an insulating base, first and second lands arranged, and an intermediate part arranged between the first and second lands. The first and second light emitting elements are flip-chip mounted on the first and second lands, respectively. The light reflective covering member is provided above the intermediate part and covers lateral surfaces of the first and second light emitting elements. The light reflective covering member defines a recess part arranged above the intermediate part with a bottom of the recess part being positioned below top surfaces of the first and second light emitting elements and above the top surface of the intermediate part, and a surface of the light reflective covering member defining the recess part constitutes a part of an outer surface of the light emitting device.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: October 15, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Takuya Nakabayashi, Tadaaki Ikeda
  • Patent number: 10446421
    Abstract: Systems and methods are provided for implementing a crystal oscillator to monitor and control semiconductor fabrication processes. More specifically, a method is provided for that includes performing at least one semiconductor fabrication process on a material of an integrated circuit (IC) disposed within a processing chamber. The method further includes monitoring by at least one electronic oscillator disposed within the processing chamber for the presence or absence of a predetermined substance generated by the at least one semiconductor fabrication process. The method further includes controlling the at least one semiconductor fabrication process based on the presence or absence of the predetermined substance detected by the at least one electronic oscillator.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Cyril Cabral, Jr., Lawrence A. Clevenger, John M. Cohn, Jeffrey P. Gambino, William J. Murphy, Anthony J. Telensky
  • Patent number: 10446713
    Abstract: To remove the mask formed by nanoimprinting after dry etching. A mask is formed by nanoimprinting on a back surface of a substrate. Subsequently, dry etching is performed using chlorine gas. Dry etching is finished with the mask kept remaining. A deteriorated layer is formed on the surface of the remaining mask. The mask is irradiated with plasma generated using a mixture gas of nitrogen and oxygen. Thereby, the deteriorated layer formed on the surface of the mask is removed by evaporation. The mask is removed by dissolving in BHF (buffered hydrofluoric acid).
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: October 15, 2019
    Assignee: TOYODA GOSEI CO., LTD.
    Inventor: Kimiyasu Ide
  • Patent number: 10438864
    Abstract: A circuit package comprises a circuit device in a first epoxy mold compound and a second epoxy mold compound of different compositions.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: October 8, 2019
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Chien-Hua Chen, Michael W. Cumbie, Stephen Farrar
  • Patent number: 10424662
    Abstract: Semiconductor structures and fabrication methods thereof are provided. An exemplary semiconductor structure includes a base substrate having a first well and a second well region; a first insulation layer over the base substrate and dividing the second well region into a first region adjacent to the first well region, a second region away from the first well region and a third region under the first insulation layer; a gate structure over the base substrate in the first well region and the first region of the second well region; a first mask gate structure on a portion of the second region adjacent to the first region; a first stress layer on the first well region at a side of gate structure away from the first insulation layer; and a second stress layer on the second well regions at a side of the mask gate structure away from the isolation layer.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: September 24, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10416142
    Abstract: An optoelectronic device for detecting volatile organic compounds is described, including a die with a semiconductor body, the die forming a MOSFET transistor and at least one photodiode. The optoelectronic device is optically couplable to an optical source that emits radiation with a spectrum at least partially overlapping the absorption spectrum range of the semiconductor body. The MOSFET transistor is planar and includes a gate region and a catalytic region that is arranged on the gate region such that, in the presence of a gas mixture including volatile organic compounds, the MOSFET transistor can be biased to generate an electrical signal indicating the overall concentration of the gas mixture. The photodiode generates a photocurrent that is a function of the concentration of one or more polycyclic aromatic hydrocarbons present in the gas mixture.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: September 17, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Massimo Cataldo Mazzillo, Antonella Sciuto
  • Patent number: 10418236
    Abstract: Dielectric composite films characterized by a dielectric constant (k) of less than about 7 and having a density of at least about 2.5 g/cm3 are deposited on partially fabricated semiconductor devices to serve as etch stop layers. The dielectric composite film in one embodiment includes Al, Si, and O and has a thickness of between about 10-100 ?. The dielectric composite film can reside between two layers of inter-layer dielectric, and may be in contact with metal layers. An apparatus for depositing such dielectric composite films includes a process chamber, a conduit for delivering an aluminum containing precursor to the process chamber, a second conduit for delivering a silicon-containing precursor to the process chamber and a controller having program instructions for depositing the dielectric composite film from these precursors, e.g., by reacting the precursors adsorbed to the substrate with an oxygen-containing species.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: September 17, 2019
    Assignee: Lam Research Corporation
    Inventors: Kapu Sirish Reddy, Nagraj Shankar, Shankar Swaminathan, Meliha Gozde Rainville, Frank L. Pasquale
  • Patent number: 10411155
    Abstract: A method of producing optoelectronic semiconductor chips includes growing a semiconductor layer sequence on a growth substrate; applying at least one metallization to a contact side of the semiconductor layer sequence, which contact side faces away from the growth substrate; attaching an intermediate carrier to the semiconductor layer sequence, wherein a sacrificial layer is attached between the intermediate carrier and the semiconductor layer sequence; removing the growth substrate from the semiconductor layer sequence; structuring the semiconductor layer sequence into individual chip regions; at least partially dissolving the sacrificial layer; and subsequently removing the intermediate carrier, wherein, in removing the intermediate carrier, part of the sacrificial layer is still present, removing the intermediate carrier includes mechanically breaking remaining regions of the sacrificial layer, and the sacrificial layer is completely removed after removing the intermediate carrier.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: September 10, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Lorenzo Zini, Alexander Frey, Joachim Hertkorn, Berthold Hahn
  • Patent number: 10411102
    Abstract: A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle ?1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle ?2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: September 10, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Daisuke Kawae
  • Patent number: 10396125
    Abstract: A cross-point memory array includes a plurality of variable resistance memory cell pillars. Adjacent memory cell pillars are separated by a partially filled gap that includes a buried void. In addition, adjacent memory cell pillars include storage material elements that are at least partially interposed by the buried void.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: August 27, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Fantini, Cristina Casellato, Fabio Pellizzer