Patents Examined by Jeremy J Joy
  • Patent number: 10971681
    Abstract: A method for manufacturing an array of magnetic memory elements, wherein first memory element types are formed in a first region and second type of magnetic memory element types are formed in a second region. A shadow-mask is used during deposition to limit the deposition of at least one layer of memory element material to only the second region wherein the second memory element types are to be formed. The method can include depositing full film magnetic memory element layers over an entire substrate and then using the shadow-mask to deposit at least one performance altering material in the second memory element region. Alternatively, a first shadow-mask can be used to deposit a series of first memory element layers in a first region, and a second shadow-mask can be used to deposit a plurality of second memory element layers in a second region.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: April 6, 2021
    Assignee: SPIN MEMORY, INC.
    Inventors: Kadriye Deniz Bozdag, Eric Michael Ryan, Kuk-Hwan Kim
  • Patent number: 10957596
    Abstract: A method for fabricating caterpillar trenches for wafer dicing includes forming at least one opening within a mask formed on a substrate to protect an electronics device disposed on the substrate during isotropic etching, and isotropically etching through the at least one opening to form at least one wafer dicing channel, including laterally etching a collection of nested trenches including trenches each having a non-circular cross-section from a first surface of the substrate to a second surface of the substrate opposite the first surface.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Effendi Leobandung, Ghavam G. Shahidi
  • Patent number: 10950676
    Abstract: An array substrate includes a base substrate including a plurality of pixel regions arranged in an array, a plurality of thin film transistors distributed within respective ones of the plurality of pixel regions, each of the thin film transistors including an active layer, a gate electrode, a source electrode and a drain electrode, the drain electrode including a first portion located in a second via, a passivation layer located on the source electrodes and the drain electrodes. The passivation layer is on the first portions of the drain electrode. A plurality of pixel electrodes are distributed within respective ones of the plurality of pixel regions and located on the passivation layer. Each of the pixel electrodes are electrically connected to a respective one of the drain electrodes through a respective third via that extends through the passivation layer.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: March 16, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Hongfei Cheng
  • Patent number: 10943874
    Abstract: The stiffening brace may include a set of borders dimensioned to substantially surround an integrated circuit, wherein each border includes (1) a portion of material that is positioned atop a perimeter of the integrated circuit and (2) an additional portion of material that extends beyond the perimeter of the integrated circuit such that the additional portion of material overhangs a circuit board to which the integrated circuit is soldered. Various other apparatuses, systems, and methods are also disclosed.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: March 9, 2021
    Assignee: Juniper Networks, Inc
    Inventors: Peng Su, Valery Kugel, Jimmy Chun-Chuen Leung
  • Patent number: 10930527
    Abstract: A method for processing semiconductor wafers in a furnace is provided. The method includes forming a thin film on each of the semiconductor wafers in a furnace. The furnace includes a first end thermal zone, a middle thermal zone and a second end thermal zone arranged in sequence. The method further includes controlling the temperature of the furnace in a first thermal mode during the formation of the thin film. The method also includes supplying a purging gas into the furnace after the formation of the thin film. In addition, the method includes controlling the temperature of the furnace in a second thermal mode during the supply of the purging gas. The temperature distributions of the furnace are different in the first and second thermal modes.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Jian-Lun Lo, Jih-Churng Twu, Feng-Yu Chen, Yuan-Hsiao Su, Yi-Chi Huang, Yueh-Ting Yang, Shu-Han Chao
  • Patent number: 10923425
    Abstract: An apparatus, a method, and a method of manufacturing an integrated circuit having a metal layer, metal wires within the metal layer being configured such that they have a regular pattern.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: February 16, 2021
    Assignee: Arm Limited
    Inventors: Marlin Wayne Frederick, Jr., Karen Lee Delk
  • Patent number: 10923405
    Abstract: Embodiments include devices and methods for detecting particles, monitoring etch or deposition rates, or controlling an operation of a wafer fabrication process. In an embodiment, a particle monitoring device for particle detection includes several capacitive micro sensors mounted on a wafer substrate to detect particles under all pressure regimes, e.g., under vacuum conditions. In an embodiment, one or more capacitive micro sensors is mounted on a wafer processing tool to measure material deposition and removal rates in real-time during the wafer fabrication process. Other embodiments are also described and claimed.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: February 16, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Leonard Tedeschi, Kartik Ramaswamy, Daniel Thomas McCormick, Robert Paul Meagley
  • Patent number: 10916544
    Abstract: The present invention provides a Gate-All-Around nano-sheet complementary inverter, comprising: P-type semiconductor transistors and N-type semiconductor transistors, wherein the P-type semiconductor transistors comprise P-type semiconductor nano-sheet channels, a first gate dielectric layer fully surrounding the P-type semiconductor nano-sheet channels, a first gate electrode layer fully surrounding the first gate dielectric layer, a first source region and a first drain region, connected to two ends of the P-type semiconductor nano-sheet channel respectively, the N-type semiconductor transistors comprise N-type semiconductor nano-sheet channels, a second gate dielectric layer fully surrounding the N-type semiconductor nano-sheet channels, a second gate electrode layer fully surrounding the second gate dielectric layer, a second source region and a second drain region, connected to two ends of the N-type semiconductor nano-sheet channel respectively; and a common electrode fully surrounding the first gate el
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: February 9, 2021
    Assignee: SiEn (QingDao) Integrated Circuits Co., Ltd
    Inventor: Deyuan Xiao
  • Patent number: 10910416
    Abstract: To provide a semiconductor device, an image pickup device, and a method for manufacturing the semiconductor device that reduce wiring capacity by using gaps and maintain mechanical strength and reliability. A semiconductor device including: a multilayered wiring layer in which insulating layers and diffusion preventing layers are alternately laminated and a wiring layer is provided inside; a through-hole that is provided to penetrate through at least one or more insulating layers from one surface of the multilayered wiring layer and has an inside covered with a protective side wall; and a gap that is provided in at least one or more insulating layers immediately below the through-hole.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: February 2, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Hiroyuki Kawashima
  • Patent number: 10910599
    Abstract: A luminescent panel includes an upper sealing layer, a lower sealing layer, and an organic electroluminescent layer. The organic electroluminescent layer is provided between the upper sealing layer and the lower sealing layer and includes one or a plurality of organic electroluminescent elements. At least one of the upper sealing layer or the lower sealing layer includes one or a plurality of inorganic sealing films each provided with a plurality of fracture control parts. The fracture control parts each include an inorganic material having relatively lower mechanical strength than parts of the one or plurality of inorganic sealing films other than the fracture control parts.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: February 2, 2021
    Assignee: JOLED INC.
    Inventor: Atsushi Sasaki
  • Patent number: 10897819
    Abstract: A display panel, a flexible circuit board and a display device are provided. The display panel includes a substrate, and at least one row of a plurality of input pads including at least one first-input pad disposed in the middle of the input pads and a plurality of second-input pads disposed on both sides of the first input pad. Each input pad includes a first end and a second end that are oppositely disposed, and a spacing between any adjacent two input pads includes a first spacing between adjacent two first ends and a second spacing between adjacent two second ends. The first spacing and the second spacing between any adjacent two second-input pads are not equal. Along a direction from the first-input pad to the second-input pad, starting from adjacent first-input and second-input pads, the first spacing and the second spacing successively and gradually increases, respectively.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: January 19, 2021
    Assignee: XIAMEN TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Huangyao Wu, Shumao Wu, Guochang Lai
  • Patent number: 10896914
    Abstract: A semiconductor memory device comprises: a substrate; gate electrodes arranged in a first direction crossing a surface of the substrate; a first semiconductor layer including a first portion extending in the first direction and facing the plurality of gate electrodes, and, a second portion nearer to the substrate than the first portion; a gate insulating film provided between the gate electrode and the first portion of the first semiconductor layer, and, including a memory portion; and, a wiring portion provided between the substrate and the plurality of gate electrodes, connected to the second portion of the first semiconductor layer, and, extending in a second direction crossing the first direction. The wiring portion comprises a second semiconductor layer connected to the second portion of the first semiconductor layer. The second semiconductor layer includes a first crystal grain larger than a thickness in the first direction of the second semiconductor layer.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: January 19, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Tachikawa, Hidenori Miyagawa
  • Patent number: 10897021
    Abstract: A display device including a display panel having a display area and a non-display area, the non-display area being disposed at a peripheral portion of the display area and having a bending area; an integrated circuit (IC) disposed in the non-display area to drive the display panel; a first layer formed between the display area and the IC and covering the bending area; and a first member covering the IC and the first layer and overlapping with the bending area.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: January 19, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventor: Kyu Bong Jung
  • Patent number: 10896977
    Abstract: A novel material and a transistor including the novel material are provided. One embodiment of the present invention is a composite oxide including at least two regions. One of the regions includes In, Zn and an element M1 (the element M1 is one or more of Al, Ga, Si, B, Y, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be, and Cu) and the other of the regions includes In, Zn, and an element M2 (the element M2 is one or more of Al, Ga, Si, B, Y, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be, and Cu). In an analysis of the composite oxide by energy dispersive X-ray spectroscopy, the detected concentration of the element M1 in a first region is less than the detected concentration of the element M2 in a second region, and a surrounding portion of the first region is unclear in an observed mapping image of the energy dispersive X-ray spectroscopy.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: January 19, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10896821
    Abstract: Methods for reducing warpage of bowed semiconductor substrates, particularly saddle-shaped bowed semiconductor substrates, are provided herein. Methods involve depositing a bow compensation layer by physical vapor deposition on the backside of the bowed semiconductor substrate in regions to form a compressive film on a tensile substrate and a tensile film on a compressive substrate. Methods involve sputtering material onto a backside of a substrate using a shadow mask or by using more than one target and rotating the semiconductor substrate being sputtering operations.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: January 19, 2021
    Assignee: Lam Research Corporation
    Inventor: Chanyuan Liu
  • Patent number: 10896953
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high voltage diode structures and methods of manufacture. The structure includes: a diode structure composed of first well of a first dopant type in a substrate; and a well ring structure of the first dopant type in the substrate which completely surrounds the first well of the first dopant type, and spaced a distance “x” from the first well to cut a leakage path to a shallower second well of a second dopant type.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: January 19, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jagar Singh, Shiv Kumar Mishra
  • Patent number: 10886192
    Abstract: A semiconductor package includes a first semiconductor package including a core member having a through-hole, a first semiconductor chip disposed in the through-hole and having an active surface with a connection pad disposed thereon, a first encapsulant for encapsulating at least a portion of the first semiconductor chip, and a connection member disposed on the active surface of the first semiconductor chip and including a redistribution layer electrically connected to the connection pad of the first semiconductor chip, a second semiconductor package disposed on the first semiconductor package and including a wiring substrate electrically connected to the connection member, at least one second semiconductor chip disposed on the wiring substrate, and a second encapsulant for encapsulating at least a portion of the second semiconductor chip, and a heat dissipation member covering a lateral surface of the second semiconductor package and exposing an upper surface of the second encapsulant.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: January 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Hyun Lim, Han Kim, Yoon Seok Seo, Sang Jong Lee
  • Patent number: 10879229
    Abstract: A method of forming an integrated circuit structure includes placing a tap cell layout pattern on a layout level, placing a set of standard cell layout patterns adjacent to the tap cell layout pattern, and manufacturing the integrated circuit structure based on at least one of the layout patterns. The placing the first well layout pattern includes placing a first layout pattern extending in a first direction and having a first width, placing a second layout pattern adjacent to the first layout pattern, and having a second width greater than the first width, and placing a first implant layout pattern on a second layout level, extending in the first direction, overlapping the first layout pattern and having a third width greater than the first width.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kam-Tou Sio, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Yi-Hsun Chiu
  • Patent number: 10872838
    Abstract: Techniques are described to limit heat transfer from a first electronic component to a second electronic such as by having an aperture in a lid over the second electronic component to form a gap in the conductance of heat from the first electronic component to the second electronic component. A semiconductor electronic package includes a substrate, a first electronic component that is of a first type and that is mounted along a surface of the substrate, a second electronic component that is of a second type different than the first type and that is mounted along the surface of the substrate, and a metallic component that is positioned over the first electronic component and that has an aperture through which the second electronic component is exposed.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: December 22, 2020
    Assignee: Juniper Networks, Inc.
    Inventors: Alexander I. Yatskov, Gautam Ganguly
  • Patent number: 10867933
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first overlay grating over a substrate. The first overlay grating has a first strip portion and a second strip portion, and the first strip portion and the second strip portion are elongated in a first elongated axis and are spaced apart from each other. The method includes forming a layer over the first overlay grating. The layer has a first trench elongated in a second elongated axis, the second elongated axis is substantially perpendicular to the first elongated axis, and the first trench extends across the first strip portion and the second strip portion. The method includes forming a second overlay grating over the layer. The second overlay grating has a third strip portion and a fourth strip portion.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Long-Yi Chen, Jia-Hong Chu, Chi-Wen Lai, Chia-Ching Liang, Kai-Hsiung Chen, Yu-Ching Wang, Po-Chung Cheng, Hsin-Chin Lin, Meng-Wei Chen, Kuei-Shun Chen