Abstract: A method for forming a semiconductor structure includes forming a dielectric layer on a substrate, including a first region and a second region; forming a first gate opening and a second gate opening in dielectric layer of the first region and the second region, respectively; forming initial work function layers on bottom and sidewall surfaces of the first gate opening and the second gate opening; and performing at least one cycle of a combined etching process to etch the initial work function layers formed in the first gate opening and form a work function layer in the second gate opening from the initial work function layers. Each cycle of the combined etching process includes performing an oxide etching process to etch the initial work function layers; and then performing a main etching process on the initial work function layers to remove an exposed initial work function layer.

Abstract: A semiconductor device includes a first raised feature in a NFET region on a substrate, a first n-type doped epitaxial semiconductor material grown on the first raised feature, the first n-type doped epitaxial material having a first upward facing surface and a first downward facing surface, a first contact metal on the first downward facing surface, and a second contact metal on the first upward facing surface. The device further includes a second raised feature in a PFET region on the substrate, a second p-type doped epitaxial semiconductor material grown on the second raised feature, the second p-type doped epitaxial material having a second upward facing surface and a second downward facing surface, a third contact metal on the second downward facing surface, and a fourth contact metal on the second upward facing surface, wherein the fourth contact metal is different from the second contact metal.

Abstract: A thin film package structure, a thin film package method, and a display panel are disclosed. The thin film package structure includes a substrate, an organic adhesive layer, and a package film layer. The package film layer covers the substrate and the organic adhesive layer. The organic adhesive layer in the non-display region is designed to have a groove structure and an embankment structure defined by the groove structure. The groove structure and the embankment structure surround the display region. At least one of the groove structures and the embankment structure is a structure extending in a zigzag form or a grid-shaped structure. The organic adhesive layer is disposed in the non-display region of the substrate, and is designed to have multiple zigzagging or grid-shaped groove structures.

Abstract: A method of forming a semiconductor structure including: forming a drift well in a substrate, in which the drift well includes first dopants having a first conductivity type; forming an isolation structure over the drift well; forming a well region in the drift well and spaced apart from the isolation structure, such that a top portion of the drift well is between the well region and the isolation structure; doping the top portion with second dopants having a second conductivity type different from the first conductivity type, such that a doping concentration of the second dopants in the top portion is lower than a doping concentration of the first dopants in the top portion after doping the top portion; and forming a gate structure extending from the isolation structure to the well region and covering the top portion of the drift well.

Abstract: A layered structure for semiconductor application is described herein. The layered structure includes a starting material and a fully depleted porous layer formed over the starting material with high resistivity. In some embodiments, the layered structure further includes epitaxial layer grown over the fully depleted porous layer. Additionally, a process of making the layered structure including forming the fully depleted porous layer and epitaxial layer grown over the porous layer is described herein.

Abstract: A semiconductor device includes a leadframe, a semiconductor die attached to the leadframe, and an encapsulation material encapsulating the semiconductor die and a portion of the leadframe. The leadframe includes a first main face and a second main face opposite to the first main face. The leadframe includes leads wherein each lead includes a fully plated end face extending between an unplated first sidewall and an unplated second sidewall opposite to the first sidewall. The end face and the first and second sidewalls of each lead are perpendicular to the first and second main faces.

Abstract: A semiconductor device includes a substrate, a first fin, and a second fin. The first and second fins are spaced apart from each other in a first direction on the substrate and extend in a second direction intersecting the first direction. The semiconductor device further includes a first shallow trench formed between the first and second fins, and a field insulating film which fills at least a part of the first shallow trench. The field insulating film includes a first portion, a second portion adjacent to the first portion, and a third portion adjacent to the second portion and adjacent to a side wall of the first shallow trench. The first portion includes a central portion of an upper surface of the field insulating film in the first direction. The upper surface of the field insulating film is in a shape of a brace recessed toward the substrate.

Abstract: A flexible organic light emitting diode (OLED) panel is provided. The flexible OLED panel includes a flexible substrate including a light emitting region, a thinned region, and a wiring region, wherein the light emitting region is adjacent to the wiring region, the thinned region is disposed between the light emitting region and the wiring region, and the thinned region includes: a substrate groove; and a first ductile material disposed in the substrate; a plurality of metal wires disposed on the light emitting region and the wiring region of the flexible substrate; a light emitting layer disposed on one of the metal wires, and the light emitting layer located in the light emitting region; and an encapsulation layer disposed on the light emitting layer, and the encapsulation layer including an encapsulation-layer groove located in the thinned region, wherein the encapsulation-layer groove is opposite to the substrate groove.

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer provided on a portion of the first semiconductor layer, a third semiconductor layer provided on a portion of the second semiconductor layer and separated from the first semiconductor layer, a fourth semiconductor layer provided on an other portion of the first semiconductor layer, a first insulating film provided on a portion between the third semiconductor layer and the fourth semiconductor layer and on a portion of the fourth semiconductor layer at the second semiconductor layer side, a second insulating film contacting the first insulating film, a third insulating film provided above the second insulating film, and an electrode provided on the first insulating film, on the second insulating film, and on the third insulating film. The second insulating film is provided on the fourth semiconductor layer, and is thicker than the first insulating film.

Abstract: The present disclosure is directed to a semiconductor package including a substrate having a lower surface with a plurality of slot structures. The plurality of slot structures are multi-layer structures that encourage the formation of solder joints. The semiconductor package is desirable for high reliability applications in which each solder joint termination should be checked by visual systems to ensure a proper electrical connection has been made.

Abstract: Various semiconductor chips with solder capped probe test pads are disclosed. In accordance with one aspect of the present invention, a semiconductor chip is provided that includes a substrate, plural input/output (I/O) structures on the substrate and plural test pads on the substrate. Each of the test pads includes a first conductor pad and a first solder cap on the first conductor pad.

Abstract: According to one example, a method includes performing a Chemical Mechanical Polishing (CMP) process on a semiconductor workpiece that includes a nanosheet region, the nanosheet region having alternating layers of a first type of semiconductor material and a second type of semiconductor material. The method further includes stopping the CMP process when the first type of semiconductor material is covered by the second type of semiconductor material, patterning the nanosheet region to form nanosheet stacks, forming an isolation structure around the nanosheet stacks, removing a top layer of the second type of semiconductor material from the nanosheet stacks, recessing the isolation structure, and forming a gate structure over the nanosheet stacks.

Abstract: A method includes depositing a dummy gate dielectric layer over a semiconductor region, depositing a dummy gate electrode layer, and performing a first etching process. An upper portion of the dummy gate electrode layer is etched to form an upper portion of a dummy gate electrode. The method further includes forming a protection layer on sidewalls of the upper portion of the dummy gate electrode, and performing a second etching process. A lower portion of the dummy gate electrode layer is etched to form a lower portion of the dummy gate electrode. A third etching process is then performed to etch the lower portion of the dummy gate electrode using the protection layer as an etching mask. The dummy gate electrode is tapered by the third etching process. The protection layer is removed, and the dummy gate electrode is replaced with a replacement gate electrode.

Abstract: According to various embodiments, a transistor device may include a substrate. The transistor device may further include a drain terminal and a source terminal formed in the substrate, and a gate terminal formed over the substrate. The transistor device may further include an insulator structure arranged between the drain terminal and the source terminal, and at least partially under the gate terminal. The insulator structure may include an oxide member and a trench isolation region. The oxide member may be at least partially formed over the trench isolation region.

Abstract: A display apparatus includes a substrate including a display area including a main display area and an edge display area extended directly from a side of the main display area, and a peripheral area outside the display area and including a pad area through which electrical signals are applied to the display area; and in the peripheral area, a plurality of wirings between the display area and the pad area and through which the electrical signals are transmitted from the pad area to the display area, the plurality of wirings including: a first wiring through which an electrical signal is transmitted from the pad area to the main display area, and a second wiring through which an electrical signal is transmitted from the pad area to the edge display area, where an electrical resistance per unit length of the first wiring is greater than that of the second wiring.

Abstract: A fin field effect transistor device structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes a cap layer formed over the gate structure. The structure also includes a contact structure formed over the gate structure penetrating through the cap layer. The structure also includes an isolation film formed over sidewalls of the contact structure. The isolation film is separated from the gate structure, and a bottom surface of the isolation film is below a top surface of the cap layer.

Abstract: A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle ?1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle ?2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

Abstract: There is provided a technique for suppressing the operation of a parasitic transistor in a semiconductor device having a voltage sense structure. The semiconductor device includes: a semiconductor layer; a first impurity region; a second impurity region; a first semiconductor region; a second semiconductor region; a first electrode; a second electrode; and a third electrode. The second impurity region includes a low lifetime region at least under the second semiconductor region. The low lifetime region is a region having a defect density higher than that in a surface layer of the second impurity region or a region in which a heavy metal is diffused.

Abstract: A semiconductor package includes a semiconductor die having a first surface and a second surface opposite to the first surface, a conductive wiring layer stacked with the semiconductor die and proximal to the first surface, an encapsulant encapsulating the semiconductor die and stacked with the conductive wiring layer, and a replacement structure exposing from the encapsulant and being free of fillers. A method for manufacturing the semiconductor package is also disclosed in the present disclosure.

Abstract: A semiconductor device including: a substrate including a first active region; a first active pattern on the first active region; a gate electrode intersecting the first active pattern and extending in a first direction; a first source/drain pattern on the first active pattern, the first source/drain pattern adjacent to the gate electrode; a first interlayer insulating layer covering the gate electrode and the first source/drain pattern; and an active contact penetrating the first interlayer insulating layer to be electrically connected to the first source/drain pattern, wherein the active contact extends in the first direction, wherein a top surface of the active contact includes: a first protrusion; a second protrusion; and a first depression between the first and second protrusions.