Patents Examined by Jermele Hollington
  • Patent number: 7570074
    Abstract: An induction motor having a rotor and a stator is protected during running overloads by connecting the motor to an overload protection relay that can be tripped to interrupt power to the motor in the event of an overload, tracking the stator winding temperature of the motor during running overloads with a hybrid thermal model by online adjustment in the hybrid thermal model, and tripping the overload protection relay in response to a predetermined running overload condition represented by the tracked stator winding temperature. In one embodiment of the invention, the stator winding temperature is tracked by use of an online hybrid thermal model that uses the resistance of the rotor as an indicator of rotor temperature and thus of the thermal operating conditions of the motor. The hybrid thermal model incorporates rotor losses and heat transfer between the rotor and the stator, and approximates the thermal characteristics of the rotor and stator.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: August 4, 2009
    Assignee: Square D Company
    Inventors: Zhi Gao, Thomas G. Habetler, Ronald G. Harley, Roy Stephen Colby
  • Patent number: 7382150
    Abstract: A sensitivity switchable detection circuit includes a high gain circuit for outputting a first signal, a low gain circuit for outputting a second signal, and an output switching circuit for switching between the first signal and the second signal. When the first signal is smaller than a lower limit, the first signal determines a detected signal. When the second signal is larger than an upper limit, the second signal determines the detected signal. When the first signal is larger than the lower limit and the second signal is lower than the upper limit, a weighting function that uses the first signal and the second signal as input variables determines the detected signal.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: June 3, 2008
    Assignee: Denso Corporation
    Inventors: Yutaka Ohashi, Jirou Hayashi
  • Patent number: 7378834
    Abstract: An electronic assembly tester for testing an electrical component of an optoelectronic device. The electrical component includes a transmit and receive port. The tester includes of a base, an arm, and a hinge. The arm includes a flex circuit and cables. The arm is rotated into a closed position to form a temporary electrical connection between the electrical component and the flex circuit. Other configurations for forming a temporary electrical connection between the test circuit and the electrical component are possible. The electrical component is evaluated by providing a data signal to the transmit portion of the electrical component and evaluating a return data signal obtained from the receive portion of the electrical component.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: May 27, 2008
    Assignee: Finisar Corporation
    Inventors: Rudolf J. Hofmeister, Konstantinos G. Haritos, John C. Dirkson, Samantha R. Bench
  • Patent number: 7375543
    Abstract: The present invention provides a system and method for electrostatic discharge (ESD) testing. The system includes a circuit that has a switch coupled to an input/output (I/O) circuit of a device under test (DUT), a charge source coupled to the switch, and a control circuit coupled to the switch, wherein the control circuit turns on the switch to discharge an ESD current from the charge source to the I/O circuit, and wherein the circuit is integrated into the DUT. According to the system and method disclosed herein, the system provides on-chip ESD testing of a DUT without requiring expensive and specialized test equipment.
    Type: Grant
    Filed: July 21, 2005
    Date of Patent: May 20, 2008
    Assignee: LSI Corporation
    Inventors: Choshu Ito, William M. Loh, Jau-Wen Chen
  • Patent number: 7372251
    Abstract: A semiconductor integrated circuit has a memory operating on a first clock. A memory device captures first output data, being output from the memory in synchronization with the first clock, depending on a second clock having a frequency equal to or less than the first clock. An expected value comparison section, operating on the second clock, compares second output data being output from the memory device and third output data being output from the memory immediately after the output of the first output data with a predetermined expected value.
    Type: Grant
    Filed: June 2, 2005
    Date of Patent: May 13, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Osamu Ichikawa
  • Patent number: 7372289
    Abstract: A semiconductor integrated circuit device, i.e. a reset IC(1), includes: a detection circuit (4) for detecting whether an input voltage (Vin) has risen or dropped by comparing the input voltage (Vin) with a reference voltage; a delay circuit (8) for delaying a start-up voltage detection signal from the detection circuit (4) by charging a capacitor (C) connected thereto via a connection terminal (CT), and discharging the capacitor (C) by receiving an output signal (Vout) of a first voltage; a retention circuit (9) for retaining a start-up voltage detection signal delayed by the delay circuit (8); and a driver (10) for generating an output signal (Vout) that becomes a first voltage by a start-up voltage detection signal retained by the retention circuit (9), and generating an output signal (Vout) that becomes a second voltage by a voltage drop detection signal from the detection circuit (4).
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: May 13, 2008
    Assignee: Rohm Co., Ltd.
    Inventor: Kenichi Hirooka
  • Patent number: 7368927
    Abstract: A probe head including an elastic membrane capable of exerting a restoring force when one of the surfaces of the elastic membrane is distorted. A conductive probe includes a beam having a first end and a second end, with a probe tip proximate the first end for contacting a device under test. A beam contact proximate the second end of the beam. The beam being movable to deform at least one surface of the elastic membrane.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: May 6, 2008
    Assignee: Cascade Microtech, Inc.
    Inventors: Kenneth Smith, Michael Jolley, Victoria Van Syckel
  • Patent number: 7362115
    Abstract: An improved chuck assembly with lift pins. The chuck assembly may have an outer periphery and an upper surface. The lift pins may be positioned within the periphery of the chuck assembly and may be capable of relative vertical movement with respect to the upper surface of the chuck assembly.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: April 22, 2008
    Assignee: Cascade Microtech, Inc.
    Inventors: Peter Andrews, Brad Froemke, John Dunklee
  • Patent number: 7362121
    Abstract: A system replicates the rapid temperature increases that are believed to cause microbump failures in certain applications of programmable logic devices (PLDs). The system configures a PLD under test with a circuit that switches a large amount of current and generates a large amount of heat when the circuit is clocked. The system monitors the temperature of the PLD and controls the switching of the circuit to achieve a predetermined temperature within a predetermined time period. The PLD is cooled, and the thermal cycling is repeated. The system detects microbump failures and communicates failure data to a computer for logging and analysis.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: April 22, 2008
    Assignee: Xilinx, Inc.
    Inventors: Robert O. Conn, Steven J. Carey, Siuki Chan, William H. Pabst
  • Patent number: 7355426
    Abstract: The invention relates to a universal measuring adapter system for adapting or contacting semiconductor components in the most varied packages for electrically operating and measuring the same. The pins or contact pads of the package are electrically contacted on the input side in a specially adapted socket, and the socket, on the side of the device (output side), has contact pins whose pin assignment corresponds to the pin assignment of the package contacted inside the socket. The aim of the invention is to create a universal measuring system for adapting or contacting semiconductor components in the most varied packages for electrically operating, measuring and analyzing the same, with which, on the side of the device, the pin numbers can always be tapped at the same location regardless of the package and which is suited for expansion stages with any number of pins and pin configurations.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: April 8, 2008
    Assignee: Infineon Technologies AG
    Inventors: Isa Ahmad, Christian Burmer, Anton Stuffer
  • Patent number: 7355422
    Abstract: A novel probe card that comprises a set of fiducials and a method for using the same are disclosed. The set of fiducials comprises a first fiducial and a second fiducial fixed relative to the probe card substrate. Comparing the relative positions of the fiducials determines whether the probes are in proper alignment. This can be performed by the unaided eye or by using a low powered microscope. This novel probe card may also be used with computer vision alignment methods, thus enhancing the speed and accuracy of the computer vision method.
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: April 8, 2008
    Assignee: Touchdown Technologies, Inc.
    Inventor: Steven J Walker
  • Patent number: 7348768
    Abstract: Provided is a tray transfer apparatus having a transfer plate arranged and configured to support a tray containing a number of semiconductor devices in an array of pockets. The tray transfer apparatus further includes a driving means arranged and configured for the movement and positioning of the transfer plate. The transfer plate is provided with a plurality of tray holders that may be selectively engaged to support a tray and with detecting means corresponding to the array of pockets provided in a supported tray. In instances in which one or more of the detecting means sense the presence of more than one semiconductor device in a corresponding pocket of a supported tray, the tray transfer apparatus will generate an alarm signal and/or suspend operation so that corrective measures may be taken.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: March 25, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Eun-Soo Lee
  • Patent number: 7345493
    Abstract: Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate having active electronic components such as ASICs mounted to an interconnection substrate or incorporated therein, metallic spring contact elements effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) on a wafer-under-test (WUT), all disposed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. The spring contact elements may be mounted to either the DUTs or to the ASICs, and may fan out to relax tolerance constraints on aligning and interconnecting the ASICs and the DUTs. Physical alignment techniques are also described.
    Type: Grant
    Filed: July 18, 2006
    Date of Patent: March 18, 2008
    Assignee: FormFactor, Inc.
    Inventors: Igor Y. Khandros, David V. Pedersen
  • Patent number: 7345466
    Abstract: A cleaning device for use in a semiconductor processing. The device comprises a substrate supporter for supporting a substrate to be cleaned, a scrub pad mounting plate, and a chuck coupling to the substrate supporter and the scrub pad mounting plate. The chuck is configured to move the substrate supporter and the scrub pad mounting plate. The device further comprises a scrub pad mountable to and moveable from the scrub pad mounting plate. The scrub pad, when mounted to the scrub pad mounting plate, is higher than the substrate when mounted on the substrate supporter. The scrub pad mounting plate and the substrate supporter can both be coupled to the chuck so that the chuck moves both the scrub pad mounting plate and the substrate supporter in one action.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: March 18, 2008
    Assignee: Electroglas, Inc.
    Inventors: Michael Vogtmann, Rolf Hagenlocher, Uday Nayak
  • Patent number: 7336090
    Abstract: Systems and methods for frequency specific closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a frequency specific predetermined value of a dynamic operating indicator of the integrated circuit at the desired specific operating frequency. The predetermined value is stored in a data structure within a computer usable media. The data structure comprises a plurality of frequency specific predetermined values for a variety of operating frequencies. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the measured behavior of the integrated circuit.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: February 26, 2008
    Assignee: Transmeta Corporation
    Inventors: Kleanthes G. Koniaris, James B. Burr
  • Patent number: 7336092
    Abstract: Systems and methods for closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a predetermined value of a dynamic operating indicator of the integrated circuit. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the integrated circuit's behavior.
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: February 26, 2008
    Assignee: Transmeta Corporation
    Inventors: Kleanthes G. Koniaris, James B. Burr
  • Patent number: 7332918
    Abstract: A prober which tests an object to be tested under temperature control is provided. This prober includes a stage base, Z stage, X-Y stage having a frame structure, substrate fixing mechanism arranged on the X-Y stage, a probe card arranged to oppose the substrate fixing mechanism, and a probing stage fixed on the Z stage and arranged in the frame structure of the X-Y stage such that its axis coincides with an extension line vertically extending from the probe center of the probe card. The probing stage includes a probing elevating mechanism, and a temperature controller to heat and cool the object to be tested. The probing stage supports the substrate of the object to be tested from the bottom surface, and controls the temperature of the object to be tested.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: February 19, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Masahiko Sugiyama, Yoshinori Inoue
  • Patent number: 7332906
    Abstract: A method monitors a vacuum interrupter for leakage or loss of vacuum. The vacuum interrupter includes a line side, a load side and separable contacts electrically connected therebetween. The line side has a line side voltage and the load side has a load side voltage. The method includes determining whether the separable contacts of the vacuum interrupter are intended to be open or closed, comparing the line side voltage to the load side voltage, and determining the leakage or the loss of vacuum when the separable contacts of the vacuum interrupter are intended to be open and when the load side voltage is within a predetermined amount of the line side voltage.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: February 19, 2008
    Assignee: Eaton Corporation
    Inventors: Francois J. Marchand, James J. Benke, Russell W. Long
  • Patent number: 7332919
    Abstract: One embodiment of the present invention provides a system for distributing signals through a jig-plate in a computer system. The jig-plate contains alignment features that assist in positioning semiconductor chips in relation to the jig-plate. In addition, the jig-plate contains one or more embedded signal routing layers. These metal routing layers provide one or more signal routes for the distribution of signals through the jig-plate to semiconductor chips which have been aligned with the jig-plate. Note that routing the signals through the jig-plate facilitates the distribution of the signals without requiring that the signals be routed through the semiconductor chips in the jig-plate.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: February 19, 2008
    Assignee: Sun Microsystems, Inc.
    Inventors: Ronald Ho, Robert J. Drost, Arthur R. Zingher
  • Patent number: 7330022
    Abstract: A power monitoring system for electrical panels providing power, received from one or more power sources, to multiple current conductors. The power monitoring system preferably includes a plurality of sensors affixed to a support. A portion of each sensor defines an opening through which a current conductor may be extended.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: February 12, 2008
    Assignee: Veris Industries, LLC
    Inventors: Marc Bowman, David Bruno, Marshall Mauney