Abstract: The present invention provides a semiconductor integrated circuit capable of testing a high-speed memory at the actual operation speed of the memory even when the operation speed of the built-in self-test circuit of the integrated circuit is restricted. In order to test a memory operating on a first clock, the integrated circuit is provided with a first test pattern generation section, operating on a second clock, for generating test data, and a second test pattern generation section, operating on a third clock, the inverted clock of the second clock, for generating test data. Furthermore, the integrated circuit is provided with a test data selection section for selectively outputting either the test data output from the first test pattern generation section or the test data output from the second test pattern generation section depending on the signal value of the second clock, thereby inputting the test data to the memory as test data.

Abstract: A chip-scale packaged IC is made by bonding one or more singulated die chips (from an IC wafer) to a common substrate, such as a single cap wafer (or a portion thereof) and cutting (singulating) the substrate to yield individual, chip-scale packaged ICs. Alternatively, each die chip is bonded to an individual, pre-cut cap. Electrically conductive paths extend through the cap wafer, between wafer contact pads on the surface of the cap and electrical contact points on the IC wafer. Optionally, the cap wafer contains one or more die. The IC wafer can be fabricated according to a different technology than the cap wafer, thereby forming a hybrid chip-scale packaged IC. Optionally, additional “upper-level” cap wafers (with or without die) can be stacked to form a “multi-story” IC.

Abstract: A power supply assembly includes a dielectric substrate and a power supply circuit supported by the dielectric substrate. A conductive connection block is attached to the dielectric substrate at a main surface thereof and is connected to a power supply terminal of the power supply circuit. A spring probe pin is fitted in a bore formed in the connection block and includes a conductive sleeve and a conductive plunger fitted in the sleeve. The conductive sleeve is in electrically conductive contact with the connection block.

Abstract: Provided is a membrane with bumps whose variations in shape are minimized to a least extent and which are capable of supporting a micro electrical circuit. The membrane with bumps includes: a plurality of bumps, each of which is made up of a probe and an electrode, with the probe having a diameter which becomes smaller from one end toward another end of the probe, and with the electrode having a diameter which is larger than the diameter of the one end of the probe; and an insulating base where the bumps are positioned at predetermined locations so that the bumps are insulated from each other, wherein the probe is positioned, penetrating the insulating base in a thickness direction, and a metal film is placed between the electrode and the insulating base.

Abstract: System and apparatus enabling the use of a single cable to communicate triggering information between each of a plurality of signal acquisition devices and, illustratively, an external trigger control unit. A combined trigger signal is produced only when each trigger condition of each signal acquisition device is true. Thus, all of the signal acquisition devices will be triggered substantially simultaneously.

Abstract: A testing assembly for an electrical test of an electronic package is provided. The testing assembly includes a testing circuit board and a testing socket mounted thereon. The testing socket includes an insulating body and a plurality of pins. The insulating body has a holding surface for supporting a contact surface of the electronic package, and at least one low-dielectric constant region located between two neighboring pins, and the dielectric constant of the low-electric constant region is lower than other regions of the insulating body. In addition, the pins passing through the insulating body are configured as the electric channels between a plurality of contacts on the contact surface and a plurality of testing pads on a conductive layer on a surface of the testing circuit board. Furthermore, the pins include a signal pin, and one end of the signal pin is electrically coupled to the signal testing pad.

Abstract: System and method for integrated circuit manufacturing. A preferred embodiment comprises transmitting a first set of data to integrated circuits (ICs) while they are in an on-wafer state and having each IC store the first set of data into memory, transmitting a second set of data to the ICs and having the ICs compare the second set of data with the first set of data stored in the memory, reading out the results of the comparisons, and marking an IC as being defective if the comparison indicates that that the first set of data did not match the second set of data. Each IC features an antenna formed in the scribe line region adjacent to the IC so that communications can take place while the IC remains on the wafer without the need to use electrical probes.

Abstract: Provided is an apparatus for establishing a distance between a test head and a peripheral. The apparatus includes a frame to which one of either a test head or a peripheral is docked. The frame has a linear unit which moves the frame towards or away from a docking surface of either the test head or the peripheral.

Abstract: A probe needle apparatus and method provides a drive guard having the same potential as a probe needle for reducing signal noise in low current measurements. The probe needle apparatus includes a conductive central core covered with alternating layers of dielectric and conductive materials, a first layer of dielectric material applied to maintain electrical access to the conductive central core while providing continuous isolation of the conductive central core elsewhere, and a conductive driven guard layer applied around the first layer of dielectric material in electrical isolation from the conductive central core.

Abstract: Described is a method for automatically generating a wafer prober file whereby testing parameters and die identities can be established for testing a complete semiconductor wafer and whereby acceptable or rejected dies can be identified and correlated later with where the good or bad dies are physically located on a wafer-under-test.

Abstract: A system, method, and apparatus are arranged to provide adaptive slope compensation in a switching regulator that includes an inductor. A control loop of the switching regulator is responsive to a ramp signal. A ramp generator that includes a capacitor circuit and a current source provides the ramp signal, where at least one of the current level of the current source and the value of the capacitor circuit are adjusted to vary the slope of the ramp signal. The adjustment of the ramp signal is responsive to at least one of: a set point for the output voltage of the switching regulator, a feedback voltage that is related to the output voltage, and a measured parameter associated with the inductor in the switching regulator. By dynamically adjusting the slope of the ramp signal, slope compensation is provided for a range of inductor values that can dynamically change during operation.

Abstract: An integrated circuit (IC) wafer includes a plurality of die and a first die indicator (FDI) formed on the wafer in a metal layer. The plurality of die include a first potentially good die and the FDI, which is detectable by a machine vision recognition system, provides a unique indication of the first potentially good die.

Abstract: According to the present invention, a method of controlling the burning in of at least one I/C device in a burn in tool is provided. For high power device, the tool has a heat sink positioned to contact each device being burned in, and has a socket for mounting each device to be burned in, and a power source to supply electrical current to burn in each device. The method includes the steps of continuously monitoring at least one process parameter selected from the group of current, voltage, power and temperature, and varying the voltage to maintain at least one of the parameters at or below a given value. Also, a technique for burning in low power devices without a heat sink is provided. The invention also contemplates a tool for performing the above method.

Abstract: A method and test configuration for performing a gross I/O functionality test at wafer sort is described. The method uses a current injector, such as a pullup or a pulldown on an I/O pad, to inject current at the I/O pad, and based on the resulting voltage, determines if the I/O characteristics of the IC meet the performance criteria set by a manufacturer. In some embodiments, the test configuration can comprise an output buffer, which can be a tristate buffer, and/or an input buffer for verifying the performance of those components. The method and test configuration allow such tests to be performed at wafer sort without a precision measurement unit and without direct access to the I/O pad to be tested.

Abstract: A wafer-level packaged IC is made by attaching a cap wafer to the top of an IC wafer before cutting the IC wafer, i.e. before singulating the plurality of die on the IC wafer. The cap wafer is mechanically attached and electrically connected to the IC wafer, then the die are singulated. Electrically conductive paths extend through the cap wafer, between wafer contact pads on the top surface of the cap and electrical contact points on the IC wafer. Optionally, the cap wafer contains one or more die. The IC wafer can be fabricated according to a different technology than the cap wafer, thereby forming a hybrid wafer-level package. Optionally, additional “upper-level” cap wafers (with or without die) can be stacked to form a “multi-story” IC.

Abstract: A semiconductor device test apparatus according to the present invention includes a circuit board 103 and a film 105. A plurality of electrodes 103c are formed at the circuit board 103 at positions that face opposite a plurality of electrodes 201a at a device to be measured 201, whereas bumps 105b are formed at the surface of the film 105 located toward the device to be measured 201, at positions that face opposite the plurality of electrodes 201a at the device to be measured 201 and electrodes 105c are formed at the surface of the film 105 located toward the circuit board 103 at positions that face opposite the plurality of electrodes 103c at the circuit board 103. The bumps 105b formed at one surface of the film 105 and the electrodes 105c formed at another surface of the film 105 are electrically connected with each other via through holes 105d to support semiconductor devices having electrodes provided at a fine pitch and to improve durability.

Abstract: Test sockets, test systems, and methods for testing microfeature devices with a substrate and a plurality of conductive interconnect elements projecting from the substrate. In one embodiment, a test socket includes a support surface and a plurality of apertures in the support surface corresponding to at least some of the interconnect elements of the microfeature device. The individual apertures extend through the test socket and are sized to receive a portion of one of the interconnect elements so that the substrate is spaced apart from the support surface when the microfeature device is received in the test socket. In one aspect of this embodiment, the individual apertures have a cross-sectional dimension less than a cross-sectional dimension of the interconnect elements so that the apertures receive only a portion of the corresponding interconnect element.

Abstract: A circuit board inspection device for inspecting the operation of a circuit board having a predetermined part or wire formed therein includes a supporting substrate disposed substantially in parallel with the parts mounting surface of the circuit board, and a signal change detection unit made of a coil or a capacitor disposed in a position of the supporting substrate corresponding to the part or wire of the circuit board, with the supporting substrate being disposed substantially in parallel with the circuit board.

Abstract: A method of testing circuit boards, in particular non-componented circuit boards in which the level of the surface of a circuit board to be tested is detected automatically in a contacting process, and the further contacting operations are then controlled on the basis of the level detected. By this process, the control of the movement of the test probes of the finger tester effects automatic matching to the level, which is of particular advantage in the testing of flexible circuit boards, since their surface may have a three-dimensional form.

Abstract: A liquid crystal substrate inspection apparatus includes an inspection device for inspecting a liquid crystal substrate and a prober replacing device disposed adjacent to the inspection device. The prober replacing device has a conveying device for conveying a prober for inspecting a liquid crystal substrate. The inspection device and the prober replacing device are arranged next to each other, so that it is possible to shorten an inspection time of the liquid crystal substrate. The prober replacing device has the conveying device for automatically conveying the prober to the inspection device.