Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.

Abstract: In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number of memory cells leakage current must be controlled. Random access memories with a dynamic threshold voltage control scheme implemented with no more than minor changes to the existing MOS process technology is disclosed. The disclosed invention controls the threshold voltage of MOS transistors. Methods for enhancing the impact of the dynamic threshold control technology using this apparatus are also included. The invention is particularly useful for DRAM and NVM devices.

Abstract: A semiconductor device has a capacitor element in which a capacitance dielectric film is disposed between an upper electrode film (upper electrode film, an upper electrode film) and a lower electrode film, and the lower electrode film has polycrystalline titanium nitride at least to a portion in contact with the capacitance dielectric film.

Abstract: In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number of memory cells leakage current must be controlled. Random access memories with a dynamic threshold voltage control scheme implemented with no more than minor changes to the existing MOS process technology is disclosed. The disclosed invention controls the threshold voltage of MOS transistors. Methods for enhancing the impact of the dynamic threshold control technology using this apparatus are also included. The invention is particularly useful for SRAM, DRAM and NVM devices.

Abstract: Provided is a spintronics device. The spintronics can include a ferromagnetic metal layer, a positive electrode disposed on a first surface portion of the ferromagnetic metal layer, and a negative electrode disposed on a second surface portion of the ferromagnetic metal.

Abstract: A semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed over the first nitride semiconductor layer; and a gate electrode facing the second nitride semiconductor layer via a gate insulating film. Because the second nitride semiconductor layer is formed by stacking plural semiconductor layers with their Al composition ratios different from each other, the Al composition ratio of the second nitride semiconductor layer changes stepwise. The semiconductor layers forming the second nitride semiconductor layer are polarized in the same direction so that, among the semiconductor layers, a semiconductor layer nearer to the gate electrode has higher (or lower) intensity of polarization.

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate in which a multi-depth trench is formed, the multi-depth trench including a shallow trench and a deep trench arranged below the shallow trench, a first dielectric material formed in partial area of the multi-depth trench, the first dielectric material including a slope in the shallow trench that extends upward from a corner where a bottom plane of the shallow trench and a sidewall of the deep trench meets, the slope being inclined with respect to the bottom plane of the shallow trench, and a second dielectric material formed in areas of the multi-depth trench in which the first dielectric material is absent.

Abstract: Bipolar memory cells and a memory device including the same are provided, the bipolar memory cells include two bipolar memory layers having opposite programming directions. The two bipolar memory layers may be connected to each other via an intermediate electrode interposed therebetween. The two bipolar memory layers may have the same structure or opposite structures.

Abstract: An embodiment is a method comprising diffusing carbon through a surface of a substrate, implanting carbon through the surface of the substrate, and annealing the substrate after the diffusing the carbon and implanting the carbon through the surface of the substrate. The substrate comprises a first gate, a gate spacer, an etch stop layer, and an inter-layer dielectric. The first gate is over a semiconductor substrate. The gate spacer is along a sidewall of the first gate. The etch stop layer is on a surface of the gate spacer and over a surface of the semiconductor substrate. The inter-layer dielectric is over the etch stop layer. The surface of the substrate comprises a surface of the inter-layer dielectric.

Abstract: A cascode gain stage apparatus includes a common-emitter connected transistor having a first base metal contact, first emitter metal contact, a first collector metal contact and a u-shaped first collector interface metal; and a common-base connected transistor having a second emitter metal contact, a second base metal contact, and a second collector metal contact, the second emitter metal contact in communication with the first collector metal contact through a transistor interconnect metallic strap, the second emitter metal contact disposed between the first collector metal contact and the second base metal contact. With this configuration, the first collector metal contact and second emitter metal contact are connected by the transistor interconnect metallic strap without high-aspect ratio traces to reduce crossover coupling.

Abstract: A method of forming a semiconductor structure. The semiconductor structure has a semiconductor substrate and an nFET and a pFET disposed upon the substrate. The pFET has a semiconductor SiGe channel region formed upon or within a surface of the semiconductor substrate and a gate dielectric having an oxide layer overlying the channel region and a high-k dielectric layer overlying the oxide layer. A gate electrode overlies the gate dielectric and has a lower metal layer abutting the high-k layer, a scavenging metal layer abutting the lower metal layer, and an upper metal layer abutting the scavenging metal layer. The metal layer scavenges oxygen from the substrate (nFET) and SiGe (pFET) interface with the oxide layer resulting in an effective reduction in Tinv and Vt of the pFET, while scaling Tinv and maintaining Vt for the nFET, resulting in the Vt of the pFET becoming closer to the Vt of a similarly constructed nFET with scaled Tinv values.

Abstract: Provided are a semiconductor device and a fabricating method of the semiconductor device. The semiconductor device may include an interlayer dielectric film formed on a substrate and including a trench, a gate insulating film formed in the trench, a first work function control film formed on the gate insulating film of the trench along bottom and sidewalls of the trench, a first metal gate pattern formed on the first work function control film of the trench and filling a portion of the trench, and a second metal gate pattern formed on the first metal gate pattern of the trench, the second metal gate pattern different from the first metal gate pattern.

Abstract: A FinFET includes a semiconductor fin supporting a first transistor and a second transistor. A first transistor gate electrode extends over a first channel region of the fin and a second transistor gate electrode extends over a second channel region of the fin. Epitaxial growth material on a top of the fin forms a raised source region on a first side of the first transistor gate electrode, an intermediate region between a second side of the first transistor gate electrode and a first side of the second transistor gate electrode, and a raised drain region on a second side of the second transistor gate electrode. The first and second transistor gate electrodes are short circuit connected to each other, with the first transistor configured to have a first threshold voltage and the second transistor configured to have a second threshold voltage different from the first threshold voltage.

Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a device isolation region, a trench formed in the device isolation region, a void connected to the trench in the device isolation region, a first mask pattern formed along sidewalls of the trench and protruding inwardly with respect to the void, a gate insulating film formed along the sidewall of the void, and a gate electrode filling the trench and at least a portion of the void.

Abstract: A semiconductor device including a gate electrode disposed on a semiconductor substrate and source/drain regions disposed at both sides of the gate electrode, the source/drain regions being formed by implanting impurities. The source/drain regions include an epitaxial layer formed by epitaxially growing a semiconductor material having a different lattice constant from that of the semiconductor substrate in a recessed position at a side of the gate electrode, and a diffusion layer disposed in a surface layer of the semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor element, a base plate having an upper surface on which the semiconductor element is mounted, a cooling fin disposed on a lower surface of the base plate, a jacket disposed in a sealing manner on the lower surface of the base plate, the jacket surrounding the cooling fin, and a header partition wall formed separately from the jacket and fixed to the jacket on the lower side of the cooling fin in the jacket, the header partition wall forming a header and a flow path for causing a refrigerant flow to the cooling fin.

Abstract: A nonvolatile semiconductor memory device that has a new structure is provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device has a plurality of memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

Abstract: The object of the present invention is to improve extraction efficiency of light of a Group III nitride-based compound semiconductor light-emitting device of a multiple quantum well structure. The device comprises a multiple quantum well structure comprising a well layer comprising a semiconductor including at least In for composition, a protective layer which comprises a semiconductor including at least Al and Ga for composition and has a band gap larger than a band gap of the well layer and is formed on and in contact with the well layer in a positive electrode side. And also the device comprises a barrier layer comprising a band gap which is larger than a band gap of the well layer and is smaller than a band gap of the protective layer, and formed on and in contact with the protective layer in a positive electrode side and a periodical structure of the well layer, the protective layer and the barrier layer.

Abstract: A metal-insulation-metal (MIM) device including a first metal layer, a first insulation layer, a second metal layer, and a second insulation layer is provided. The first insulation layer is disposed on the first metal layer. The second metal layer is disposed on a part of the first insulation layer. The second insulation layer is disposed on a side wall of the second metal layer and on another part of the first insulation layer. A width of the first insulation layer under the second metal layer and the second insulation layer parallel to the first metal layer is greater than a with of the second metal layer parallel to the first metal layer. A manufacture method of an MIM device is also provided.

Abstract: According to one embodiment, a method for manufacturing a nonvolatile storage device. The device includes a plurality of first conductive layers each extending in a first direction, a plurality of second conductive layers each extending in a second direction and spaced from the first layers, and memory cells each provided between the first layers and the second layers and including a rectifying element including a semiconductor layer, and a variable resistance element stacked with the rectifying element. The method includes a film formation step, a heating step and a patterning step. The film formation step is configured to form a rectifying element material film including an amorphous semiconductor film. The heating step is configured to heat the rectifying element material film. The patterning step is configured to form the rectifying element including the semiconductor layer by patterning the rectifying element material film after the heating step.