Abstract: A method for manufacturing a through substrate via (TSV) structure, a TSV structure, and a control method of a TSV capacitance are provided. The method for manufacturing the TSV structure includes: providing a substrate having a first surface and a second surface; forming a trench in the first surface of the substrate; filling a low resistance material into the trench; forming an insulating layer on the first surface of the substrate; forming at least one opening in the first surface of the substrate, wherein the opening is located differently the trench; forming an oxide liner layer, a barrier layer and a conductive seed layer on a sidewall and a bottom of the opening and on the insulating layer of the first surface; and filling a conductive material into the opening, wherein the opening is used to form at least one via.

Abstract: An organic photoelectronic device includes a first electrode and a second electrode facing each other, and an active layer between the first electrode and the second electrode and including a first compound represented by Chemical Formula 1 or 2, and a ratio between a FWHM of a light absorption curve depending on a wavelength of the first compound in a solution state and in a thin film state satisfies the following Relationship Equation 1: FWHM2/FWHM1<2.5. In the Relationship Equation 1, FWHM1 is a FWHM of the light absorption curve depending on a wavelength in a solution state, and FWHM2 is a FWHM of the light absorption curve depending on a wavelength in a thin film state.

Abstract: The cost of liquid phase epitaxial growth of a monocrystalline silicon carbide is reduced. A feed material 11 is such that when a surface layer thereof containing a polycrystalline silicon carbide with a 3C crystal polymorph is subjected to X-ray diffraction, a diffraction peak corresponding to a (111) crystal plane and a diffraction peak other than the diffraction peak corresponding to the (111) crystal plane are observed as diffraction peaks corresponding to the polycrystalline silicon carbide with a 3C crystal polymorph.

Abstract: In an oxide semiconductor layer, a degree of oxidation S1 of a portion located on the side of the gate insulating film, and a degree of oxidation S2 of surface layer portions located in connection regions with source and drain electrodes have a relation of S2<S1 within a range in which the oxide semiconductor layer has predetermined electric resistance, and a degree of oxidation S3 of a surface layer portion of the channel region is made higher than the degrees of oxidation S1, S2 of the other regions within the range in which the oxide semiconductor layer has the predetermined electric resistance, by annealing the oxide semiconductor layer in an oxygen-containing atmosphere after formation of the source electrode and the drain electrode.

Abstract: Disclosed are embodiments of a lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) having tapered dielectric field plates positioned laterally between conductive field plates and opposing sides of a drain drift region of the LEDMOSFET. Each dielectric field plate comprises, in whole or in part, an airgap. These field plates form plate capacitors that can create an essentially uniform horizontal electric field profile within the drain drift region so that the LEDMOSFET can exhibit a specific, relatively high, breakdown voltage (Vb). Tapered dielectric field plates that incorporate airgaps provide for better control over the creation of the uniform horizontal electric field profile within the drain drift region, as compared to tapered dielectric field plates without such airgaps and, thereby ensure that the LEDMOSFET exhibits the specific, relatively high, Vb desired. Also disclosed herein are embodiments of a method of forming such an LEDMOSFET.

Abstract: A first photoresist layer is patterned with a first pattern that includes an opening in a region between areas of two adjacent via holes to be formed. The opening in the first photoresist is transferred into a template layer to form a line trench therein. The lateral dimension of the trench is reduced by depositing a contiguous spacer layer that does not fill the trench completely. An etch-resistant material layer is conformally deposited and fills the trench, and is subsequently recessed to form an etch-resistant material portion filling the trench. A second photoresist layer is applied and patterned with a second pattern, which includes an opening that includes areas of two via holes and an area therebetween. A composite pattern of an intersection of the second pattern and the complement of the pattern of the etch-resistant material portion is transferred through the template layer.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes: a substrate; a first region over the substrate; a second region laterally adjacent to the first region; a third region disposed laterally adjacent to the second region on a side of the second region opposite the first region; a fourth region disposed within a portion of the first region proximate the second region; a fifth region disposed within a portion of the second region proximate the first region, wherein the fourth region and the fifth region are separated by a first isolation area; a sixth region disposed within a portion of the third region proximate the second region; and a seventh region disposed within the second region and below the fifth region.

Abstract: A light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. A first electrode is electrically coupled to the first conductive semiconductor layer. A current blocking layer is provided adjacent to the light emitting structure, and includes a top surface disposed in the first conductive semiconductor layer by passing through the active layer. A first metal layer is provided over the current blocking layer and contacts the first conductive semiconductor layer, and a reflective electrode is electrically coupled to the second conductive semiconductor layer.

Abstract: An array substrate, a manufacturing method thereof and a display device are provided. In the manufacturing method, the needed patterns can be formed by just three photolithography processes, wherein the semiconductor layer and the etch stop layer are formed by just one photolithography process. The method reduces one photolithography process compared to the method of the state of the art, which forms the pattern of the semiconductor layer and the etch stop layer by two photolithography processes respectively, thereby greatly reducing the manufacturing cost and improving the production efficiency.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a dummy-die paddle having a first inactive side facing up, a second inactive side facing down; forming an insulator in a single continuous structure around and in direct contact with the first inactive side; and mounting an integrated circuit over the dummy-die paddle and the insulator, the integrated circuit and the dummy-die paddle having the same coefficient of thermal expansion as the dummy-die paddle.

Abstract: An integrated circuit ESD protection circuit (270) is formed with a combination device consisting of a gated diode (271) and an output buffer MOSFET (272) where the body tie fingers of a first conductivity type (307) are formed in the substrate (301, 302) and isolated from the drain regions of a second conductivity type (310) using a plurality of diode poly fingers (231, 232) which are interleaved with a plurality of poly gate fingers (204, 205) forming the output buffer MOSFET (272).

Abstract: Methods for fabricating silicon nanowire chemical sensing devices, devices thus obtained, and methods for utilizing devices for sensing and measuring chemical concentration of selected species in a fluid are described. Devices may comprise a metal-oxide-semiconductor field-effect transistor (MOSFET) structure.

Abstract: A nonvolatile memory element of the present invention comprises a first electrode (103), a second electrode (105), and a resistance variable layer (104) disposed between the first electrode (103) and the second electrode (104), a resistance value of the resistance variable layer varying reversibly according to an electric signal applied between the electrodes (103), (105), and the resistance variable layer (104) comprises at least a tantalum oxide, and is configured to satisfy 0<x<2.5 when the tantalum oxide is represented by TaOx.

Abstract: Embodiments are directed to engineering a structure, comprising: measuring energy eigenstates of a Hamiltonian, predicting a time evolution of a combination of two energy eigenstates based on the measurement, and creating an entangled quantum state for two coefficients of the two energy eigenstates such that an associated wavefunction is encouraged to undergo the predicted time evolution.

Abstract: A semiconductor device according to an embodiment includes a first-conductive-type semiconductor substrate; a first-conductive-type first semiconductor layer formed on the semiconductor substrate, and having an impurity concentration lower than that of the semiconductor substrate; a second-conductive-type second semiconductor layer epitaxially formed on the first semiconductor layer; and a second-conductive-type third semiconductor layer epitaxially formed on the second semiconductor layer, and having an impurity concentration higher than that of the second semiconductor layer. The semiconductor device also includes a recess formed in the third semiconductor layer, and at least a corner portion of a side face and a bottom surface is located in the second semiconductor layer.

Abstract: A semiconductor device includes: a first conductivity type semiconductor substrate; and a plurality of second conductivity type semiconductor regions, the respective second conductivity type semiconductor regions being embedded in a plurality of stripe shaped trenches formed in the semiconductor substrate so that the respective second conductivity type semiconductor regions are extended in the row direction or the column direction in parallel with a first principal surface of the semiconductor substrate and are spaced in a fixed gap mutually. The semiconductor substrate and the plurality of the semiconductor regions are depleted by a depletion layer extended in the direction in parallel to the first principal surface from a plurality of pn junction interfaces, and the respective pn junction interfaces are formed between the semiconductor substrate and the plurality of the semiconductor regions.

Abstract: A NAND flash memory chip includes wide openings in an inter-poly dielectric layer through which gaps are later etched to define structures such as select gates. Such select gates are asymmetric, with inter-poly dielectric on a side adjacent to a memory cell and no inter-poly dielectric on a side away from a memory cell. Gaps etched through such openings may also define peripheral devices.

Abstract: A band heater assembly for heating an object includes a band heater that extends around at least a portion of a perimeter of the object. The band heater includes a cable and a band. The cable includes a resistive element, a first cable end and a second cable end. The resistive element generates thermal energy based on a current received from a power source. The first cable end and the second cable end are connected to respective ends of the band heater assembly. The band is connected to the cable and transfers a first portion of the thermal energy to an exterior surface of the object. At least a portion of the cable is exposed from the band heater to contact the exterior surface when the band heater assembly is connected to the object.

Abstract: A method of manufacturing a semiconductor device includes: forming a conductive film on a semiconductor substrate; patterning the conductive film in a memory region to form a first gate electrode; after forming the first gate electrode, forming a mask film above each of the conductive film in a logic region and the first gate electrode; removing the mask film in the logic region; forming a first resist film above the mask film left in the memory region and above the conductive film left in the logic region; and forming a second gate electrode in the logic region by etching the conductive film using the first resist film as a mask.

Abstract: A 3-D memory array comprises a plurality of elevationally extending strings of memory cells. An array of select devices is elevationally over and individually coupling with individual of the strings. The select devices individually comprise a channel, gate dielectric proximate the channel, and gate material proximate the gate dielectric. The individual channels are spaced from one another. The gate material comprises a plurality of gate lines running along columns of the spaced channels elevationally over the strings. Dielectric material is laterally between immediately adjacent of the gate lines. The dielectric material and the gate lines have longitudinally non-linear edges at an interface relative one another. Additional embodiments are disclosed.