Patents Examined by Jerome Jackson
  • Fabrication of field-effect transistors with atomic layer doping
    Patent number: 9048261
    Abstract: Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1020 active dopant atoms per cm3 that react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: June 2, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Young-Hee Kim, Isaac Lauer, Ramachandran Muralidhar, Dae-Gyu Park, Xinhui Wang, Min Yang
  • Semiconductor reference voltage generating device
    Patent number: 9041156
    Abstract: A reference voltage generating circuit has more than two first wells each having a first impurity concentration and more than two second wells each having a second impurity concentration different from the first impurity concentration. A first group of MOS transistors has more than two MOS transistors formed in respective ones of the first wells. A second group of MOS transistors has More than two MOS transistors formed in respective ones of the second wells.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: May 26, 2015
    Assignee: SEIKO INSTRUMENTS INC.
    Inventors: Hideo Yoshino, Hirofumi Harada, Jun Osanai
  • Unipolar heterojunction depletion-layer transistor
    Patent number: 9040956
    Abstract: A depletion-layer transistor comprising a base, an emitter and a collector, in which the emitter contains a tunnel diode which permits a tunnel current of charge carriers from the emitter in the direction of the collector when an emitter-base voltage above a first threshold voltage is applied in the direction of current flow, and in which the base contains a graphene layer.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: May 26, 2015
    Assignee: IHP GmbH—INNOVATIONS FOR HIGH PERFORMANCE MICROELECTRONICS/LEIBNIZ-INSTITUT FUR INNOVATIVE MIKROELEKTRONIK
    Inventors: Wolfgang Mehr, Gunther Lippert
  • Heterojunction transistors having barrier layer bandgaps greater than channel layer bandgaps and related methods
    Patent number: 9035354
    Abstract: A heterojunction transistor may include a channel layer comprising a Group III nitride, a barrier layer comprising a Group III nitride on the channel layer, and an energy barrier comprising a layer of a Group III nitride including indium on the channel layer such that the channel layer is between the barrier layer and the energy barrier. The barrier layer may have a bandgap greater than a bandgap of the channel layer, and a concentration of indium (In) in the energy barrier may be greater than a concentration of indium (In) in the channel layer. Related methods are also discussed.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: May 19, 2015
    Assignee: Cree, Inc.
    Inventors: Adam William Saxler, Yifeng Wu, Primit Parikh
  • Semiconductor device
    Patent number: 9024382
    Abstract: According to one embodiment, the semiconductor device includes a drift region, a first semiconductor region, a second semiconductor region, a main electrode, first gate electrodes and a second gate electrode. The first gate electrodes and the second gate electrode between a pair of first gate electrodes are provided in the drift region. The first semiconductor region is provided between the first gate electrodes and the second gate electrode. The first semiconductor region has a first side surface opposite to the one of the adjacent ones and a second side surface partially opposite to the second gate electrode. The second semiconductor region is selectively provided on the first semiconductor region. The main electrode has a portion directly adjacent to part of the second side surface and the second semiconductor region.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: May 5, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mitsuhiko Kitagawa
  • Display device
    Patent number: 9024309
    Abstract: A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, and a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the first oxide semiconductor layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: May 5, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Shigeki Komori, Hideki Uochi, Tomoya Futamura, Takahiro Kasahara
  • Methods of forming moisture barrier capacitors in semiconductor components
    Patent number: 9012297
    Abstract: Structures and methods of forming moisture barrier capacitor on a semiconductor component are disclosed. The capacitor is located on the periphery of a semiconductor chip and includes an inner plate electrically connected to a voltage node, an outer plate with fins for electrically connecting to a different voltage node.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: April 21, 2015
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Helmut Horst Tews
  • Semiconductor integrated circuit having a permanently conductive non-volatile memory element
    Patent number: 9007838
    Abstract: A semiconductor integrated circuit includes a transistor with a source region, a drain region, and a control gate electrode. The integrated circuit additionally includes a controller that selectively applies voltages to the control gate of the transistor. The controller may apply a first voltage that forms a permanent conductive path between the source and drain of the transistor.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: April 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichiro Zaitsu, Kosuke Tatsumura
  • Aligned gate-all-around structure
    Patent number: 9006829
    Abstract: Among other things, a semiconductor device comprising an aligned gate and a method for forming the semiconductor device are provided. The semiconductor device comprises a gate formed according to a multi-gate structure, such as a gate-all-around structure. A first gate portion of the gate is formed above a first channel of the semiconductor device. A second gate portion of the gate is formed below the first channel, and is aligned with the first gate portion. In an example of forming the gate, a cavity is etched within a semiconductor layer formed above a substrate. A dielectric layer is formed around at least some of the cavity to define a region of the cavity within which the second gate portion is to be formed in a self-aligned manner with the first gate portion. In this way, the semiconductor device comprises a first gate portion aligned with a second gate portion.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jean-Pierre Colinge, Kuo-Cheng Ching, Zhiqiang Wu
  • Transistors having a gate comprising a titanium nitride layer
    Patent number: 9000596
    Abstract: A MOS transistor having a gate insulator including a dielectric of high permittivity and a conductive layer including a TiN layer, wherein the nitrogen composition in the TiN layer is sub-stoichiometric in its lower portion and progressively increases to a stoichiometric composition in its upper portion.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Pierre Caubet, Sylvain Baudot
  • Semiconductor structure for substrate separation and method for manufacturing the same
    Patent number: 9000464
    Abstract: A semiconductor structure includes a temporary substrate; a first semiconductor layer positioned on the temporary substrate; a dielectric layer comprising a plurality of patterned nano-scaled protrusions disposed on the first semiconductor layer; a dielectric layer surrounding the plurality of patterned nano-scaled protrusions and disposed on the first semiconductor layer; and a second semiconductor layer positioned on the dielectric layer, wherein the top surfaces of the patterned nano-scaled protrusions are in contact with the bottom of the second semiconductor layer. An etching process is performed on the semiconductor structure to separate the first semiconductor layer and the second semiconductor layer, in order to detach the temporary substrate from the second semiconductor layer and transfer the second semiconductor layer to a permanent substrate.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: April 7, 2015
    Assignee: Design Express Limited
    Inventors: Chun-Yen Chang, Po-Min Tu, Jet-Rung Chang
  • Three dimensional pipe gate nonvolatile memory device
    Patent number: 9000509
    Abstract: A nonvolatile memory device includes a pipe gate having a pipe channel hole; a plurality of interlayer insulation layers and a plurality of gate electrodes alternately stacked over the pipe gate; a pair of columnar cell channels passing through the interlayer insulation layers and the gate electrodes and coupling a pipe channel formed in the pile channel hole; a first blocking layer and a charge trapping and charge storage layer formed on sidewalls of the columnar cell channels; and a second blocking layer formed between the first blocking layer and the plurality of gate electrodes.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: April 7, 2015
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ki-Hong Lee, Kwon Hong, Dae-Gyu Shin
  • Memory device with low reset current
    Patent number: 9000408
    Abstract: An electronic device includes a first electrode and a second electrode. The device also includes a resistive material between the first and second electrodes. An active material is between the first electrode and the resistive material. The active material is in electrical communication with the first electrode and the active material is in electrical communication with the second electrode through the resistive layer.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: April 7, 2015
    Assignee: Ovonyx, Inc.
    Inventors: Sergey Kostylev, Tyler Lowrey, Wolodymyr Czubatyj
  • GaN based semiconductor light-emitting device and method for producing same
    Patent number: 8993992
    Abstract: A GaN based semiconductor light-emitting device is provided. The light-emitting device includes a first GaN based compound semiconductor layer of an n-conductivity type; an active layer; a second GaN based compound semiconductor layer; an underlying layer composed of a GaN based compound semiconductor, the underlying layer being disposed between the first GaN based compound semiconductor layer and the active layer; and a superlattice layer composed of a GaN based compound semiconductor doped with a p-type dopant, the superlattice layer being disposed between the active layer and the second GaN based compound semiconductor layer.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: March 31, 2015
    Assignee: Sony Corporation
    Inventors: Goshi Biwa, Hiroyuki Okuyama
  • Semiconductor device
    Patent number: 8987860
    Abstract: A semiconductor device includes a substrate having a plurality of active regions defined by a device isolation region, a plurality of conductive patterns on the plurality of active regions, each of the conductive patterns having side walls, a conductive line that faces the side walls of the conductive patterns with an air spacer therebetween on the active regions, the conductive line extending in a first direction, and a first insulating film covering the side walls of the conductive patterns between the air spacer and the conductive pattern. A lower portion of the first insulating film that is near the substrate protrudes toward the air spacer.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bo-young Song, Cheol-ju Yun, Seung-hee Ko
  • Component having a via and method for manufacturing it
    Patent number: 8975118
    Abstract: An advantageous method and system for realizing electrically very reliable and mechanically extremely stable vias for components whose functionality is realized in a layer construction on a conductive substrate. The via (Vertical Interconnect Access), which is led to the back side of the component and which is used for the electrical contacting of functional elements realized in the layer construction, includes a connection area in the substrate that extends over the entire thickness of the substrate and is electrically insulated from the adjoining substrate by a trench-like insulating frame likewise extending over the entire substrate thickness. According to the present system, the trench-like insulating frame is filled up with an electrically insulating polymer.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: March 10, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Julian Gonska, Jens Frey, Heribert Weber, Eckhard Graf, Roman Schlosser
  • Integrated circuit comprising a capacitor with HSG metal electrodes
    Patent number: 8975682
    Abstract: An integrated circuit (IC) includes at least one capacitor with metal electrodes. At least one of the electrodes (10 or 30) is formed from at least surface-silicided hemispherical grain silicon or silicon alloy. A fabrication process for obtaining such a capacitor with silicided metal electrodes is also provided.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: March 10, 2015
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Aomar Halimaoui, Rebha El Farhane, Benoit Froment
  • Nonvolatile pipe gate memory device
    Patent number: 8975683
    Abstract: A nonvolatile memory device includes a pipe insulation layer having a pipe channel hole, a pipe gate disposed over the pipe insulation layer, a pair of cell strings each having a columnar cell channel, and a pipe channel coupling the columnar cell channels and surrounding inner sidewalls and a bottom of the pipe channel hole.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: March 10, 2015
    Assignee: SK Hynix Inc.
    Inventors: Ki-Hong Lee, Kwon Hong, Dae-Gyu Shin
  • Electronic device with magnetic antenna mounting
    Patent number: 8970446
    Abstract: An electronic device may have magnetically mounted antenna structures. The electronic device may have a dielectric member against which one or more antennas are mounted. The dielectric member may be a cover glass layer that covers a display in the electronic device, a dielectric antenna window, or other dielectric structure. Each antenna may have an antenna support structure. Conductive antenna structures for the antenna may be mounted to the antenna support structure. The antennas may be cavity-backed planar inverted-F antennas. Portions of each antenna support structure may be configured to receive magnets. The magnets may be attracted towards ferromagnetic structures mounted on the dielectric member. As the magnets are attracted towards the ferromagnetic structure, the antennas may be held in place against the dielectric member.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: March 3, 2015
    Assignee: Apple Inc.
    Inventors: Mattia Pascolini, Jerzy Guterman, Jonathan Haylock, Jiang Zhu, Peter Jeziorek
  • Vertical geometry InGaN LED
    Patent number: RE45517
    Abstract: A vertical geometry light emitting diode is disclosed that is capable of emitting light in the red, green, blue, violet and ultraviolet portions of the electromagnetic spectrum. The light emitting diode includes a conductive silicon carbide substrate, an InGaN quantum well, a conductive buffer layer between the substrate and the quantum well, a respective undoped gallium nitride layer on each surface of the quantum well, and ohmic contacts in a vertical geometry orientation.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: May 19, 2015
    Assignee: Cree, Inc.
    Inventors: Kathleen Marie Doverspike, John Adam Edmond, Hua-shuang Kong, Heidi Marie Dieringer, David B. Slater, Jr.