Patents Examined by Jesse Y Miyoshi
  • Patent number: 10403628
    Abstract: Embodiments of the present invention provide improved methods and structures for fabrication of capacitor-less DRAM devices, sometimes referred to as ZRAM devices. A channel is formed in a fin-type field effect transistor (finFET) that is comprised of a finned channel portion and a convex channel portion. The finned channel portion may be comprised of a first semiconductor material and the convex channel portion may be comprised of a second, different semiconductor material. In embodiments, a metal gate is disposed around the elongated surface of the channel region, but is not disposed on the short surface of the channel region. A first spacer is disposed adjacent to the gate and in direct physical contact with the short surface of the channel region, and a second spacer is disposed adjacent to the first spacer.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: September 3, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ravikumar Ramachandran, Reinaldo Ariel Vega
  • Patent number: 10373970
    Abstract: A semiconductor device structure comprises stacked tiers each comprising at least one conductive structure and at least one insulating structure longitudinally adjacent the at least one conductive structure, at least one staircase structure having steps comprising lateral ends of the stacked tiers, and at least one opening extending through the stacked tiers and continuously across an entire length of the at least one staircase structure. The at least one conductive structure of each of the stacked tiers extends continuously from at least one of the steps of the at least one staircase structure and around the at least one opening to form at least one continuous conductive path extending completely across each of the stacked tiers. Additional semiconductor device structures, methods of faulting semiconductor device structures, and electronic systems are also described.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: August 6, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Eric N. Lee
  • Patent number: 10347819
    Abstract: Methods of manufacturing a semiconductor device include forming a conductive layer on a substrate, forming an air gap or other cavity between the conductive layer and the substrate, and patterning the conductive layer to expose the air gap. The methods may further include forming conductive pillars between the substrate and the conductive layer. The air gap may be positioned between the conductive pillars.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: July 9, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jongchul Park, Byoungjae Bae, Inho Kim, Shin Kwon, Eunsun Noh, Insun Park, Sangmin Lee
  • Patent number: 10340147
    Abstract: A downsized semiconductor device having an excellent reverse characteristic, and a method of manufacturing the semiconductor device is sought to improve. The semiconductor device comprises a semiconductor body having a polygonal contour. An active area is formed in the semiconductor body. An EQR electrode is formed so as to surround the active area and to have curved portions of the EQR electrode along the corners of the semiconductor body. An interlayer insulating film is formed to cover the active area and the EQR electrode. The EQR electrode is embedded in the interlayer insulating film around the active area. EQR contacts are in contact with the curved portions of the EQR electrode and the semiconductor body outside the curved portions, and have at least side walls covered with the interlayer insulating film.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: July 2, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kouichi Murakawa
  • Patent number: 10276631
    Abstract: A method for producing a micro-LED matrix by (A) depositing an LED layer structure onto a working substrate; (B) singulating a plurality of LED structures from the LED layer structure on the working substrate; (C) applying a first contact-making structure to a carrier substrate; and (D) transferring the plurality of LED structures from the working substrate to the carrier substrate by bonding and laser lift-off. An at least two-layered carrier substrate is used, including a carrier layer and a first flexible polymer layer, in step C the first contact-making structure is applied indirectly or directly to a side of the first polymer layer which faces away from the carrier layer, and in an additional method step D-0 between method steps C and D, a second flexible polymer layer is formed at least between the singulated LED structures. A micro-LED matrix and use are also provided.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: April 30, 2019
    Assignees: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V., Albert-Ludwigs-Universität Freiburg
    Inventors: Christian Gossler, Ulrich Schwarz, Patrick Ruther
  • Patent number: 10276584
    Abstract: A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. In some embodiments, a semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Chiang Min, Tsung-Hsueh Yang, Chang-Ming Wu, Shih-Chang Liu
  • Patent number: 10249808
    Abstract: This disclosure provides systems, methods, and apparatus related to surface doping of nanostructures. In one aspect a plurality of nanostructures is fabricated with a solution-based process using a solvent. The plurality of nanostructures comprises a semiconductor. Each of the plurality of nanostructures has a surface with capping species attached to the surface. The plurality of nanostructures is mixed in the solvent with a dopant compound that includes doping species. During the mixing the capping species on the surfaces of the plurality of nanostructures are replaced by the doping species. Charge carriers are transferred between the doping species and the plurality of nanostructures.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: April 2, 2019
    Assignee: The Regents of the University of California
    Inventors: Ayaskanta Sahu, Boris Russ, Jeffrey J. Urban, Nelson E. Coates, Rachel A. Segalman, Jason D. Forster, Miao Liu, Fan Yang, Kristin A. Persson, Christopher Dames
  • Patent number: 10243058
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer including a nitride semiconductor, a first electrode separated from the first semiconductor layer in a first direction, and a first insulating film including silicon and oxygen and being provided between the first semiconductor layer and the first electrode. The first insulating film has a first thickness in the first direction. The first insulating film includes a first position, and a distance between the first position and the first semiconductor layer is ½ of the first thickness. A first hydrogen concentration of hydrogen at the first position is 2.5×1019 atoms/cm3 or less.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: March 26, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Yonehara, Hisashi Saito, Yosuke Kajiwara, Daimotsu Kato, Tatsuo Shimizu, Yasutaka Nishida
  • Patent number: 10204779
    Abstract: The present invention provides a thin film transistor and a manufacturing method thereof, an array substrate comprising the thin film transistor and a manufacturing method thereof, and a display apparatus comprising the array substrate. The manufacturing method of the thin film transistor comprises steps of forming a gate, a gate insulating layer, a semiconductor active layer, a source and a drain on a substrate, wherein the steps of forming the gate insulating layer and the semiconductor active layer comprise: preparing an insulating film, the insulating film comprises metal oxide insulating material; performing ion implantation on a predefined region of the insulating film, so that the metal oxide insulating material of partial-thickness of the insulating film in the predefined region is transformed into metal oxide semiconductor material to form the semiconductor active layer, and the rest of the insulating film forms the gate insulating layer.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: February 12, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wei Liu, Chunsheng Jiang
  • Patent number: 10205046
    Abstract: Contrary to conventional wisdom, which holds that light-emitting diodes (LEDs) should be cooled to increase efficiency, the LEDs disclosed herein are heated to increase efficiency. Heating an LED operating at low forward bias voltage (e.g., V<kBT/q) can be accomplished by injecting phonons generated by non-radiative recombination back into the LED's semiconductor lattice. This raises the temperature of the LED's active rejection, resulting in thermally assisted injection of holes and carriers into the LED's active region. This phonon recycling or thermo-electric pumping process can be promoted by heating the LED with an external source (e.g., exhaust gases or waste heat from other electrical components). It can also be achieved via internal heat generation, e.g., by thermally insulating the LED's diode structure to prevent (rather than promote) heat dissipation. In other words, trapping heat generated by the LED within the LED increases LED efficiency under certain bias conditions.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: February 12, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: Parthiban Santhanam, Dodd Joseph Gray, Rajeev Jagga Ram
  • Patent number: 10199469
    Abstract: A semiconductor device includes a silicon semiconductor layer including at least one region doped with a first conductive type dopant, a metal material layer electrically connected to the doped region, and a self-assembled monolayer (SAM) between the doped region and the metal material layer, the SAM forming a molecular dipole on an interface of the silicon semiconductor layer in a direction of reducing a Schottky barrier height (SBH).
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: February 5, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seunggeol Nam, Hyeonjin Shin, Yeonchoo Cho, Minhyun Lee, Changhyun Kim, Seongjun Park
  • Patent number: 10170471
    Abstract: A semiconductor device, having a heterogeneous silicon stack, wherein the heterogeneous silicon stack comprises at least a base layer, a doped silicon layer, and an undoped silicon layer. The semiconductor device further includes a plurality of silicon fins atop a doped silicon oxide fin layer and an undoped silicon oxide fin layer, wherein the plurality of silicon fins have a uniform width along the height of the plurality of silicon fins, and wherein the plurality of silicon fins have a plurality of hard mask caps.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Hong He, Sivananda K. Kanakasabapathy, Chiahsun Tseng, Yunpeng Yin
  • Patent number: 10131540
    Abstract: The present disclosure relates to a wafer level chip scale package (WLCSP) with a stress absorbing cap substrate. The cap substrate is bonded to a die through a bond ring and a bond pad arranged on an upper surface of the cap substrate. A through substrate via (TSV) extends from the bond pad, through the cap substrate, to a lower surface of the cap substrate. Further, recesses in the upper surface extend around the bond pad and along sidewalls of the bond ring. The recesses absorb induced stress, thereby mitigating any device offset in the die.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shao-Chi Yu, Chia-Ming Hung, Hsin-Ting Huang, Hsiang-Fu Chen, Allen Timothy Chang, Wen-Chuan Tai
  • Patent number: 10134765
    Abstract: A method for manufacturing an oxide semiconductor TFT array substrate is provided, which including: successively depositing an oxide semiconductor active layer and a transparent conductive layer on a base substrate without breaking vacuum; and forming patterns of an active layer and a transparent conductive layer. An oxide semiconductor TFT array substrate is further provided.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: November 20, 2018
    Assignees: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectronics Technology Co., Ltd.
    Inventors: Bingkun Yin, Junhao Han
  • Patent number: 10128386
    Abstract: A semiconducting structure configured to receive electromagnetic radiation, a method for manufacturing such a structure, and a semiconductor component, the semiconductor structure including: a first semiconducting area of a first type of conductivity, a second semiconducting area of a second type of conductivity opposite to the first type of conductivity, the second area being in contact with the first area to form a semiconducting junction. The second area includes a portion for which a concentration of majority carriers is at least ten times less than a concentration of majority carriers of the first area. The second area and its portion are essentially made in a first cavity configured to focus in the first cavity at least one portion of the electromagnetic radiation.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: November 13, 2018
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Francois Boulard, Roch Espiau De Lamaestre, David Fowler, Olivier Gravrand, Johan Rothman
  • Patent number: 10109647
    Abstract: A method of fabricating a high mobility semiconductor metal oxide thin film transistor including the steps of depositing a layer of semiconductor metal oxide material, depositing a blanket layer of etch-stop material on the layer of MO material, and patterning a layer of source/drain metal on the blanket layer of etch-stop material including etching the layer of source/drain metal into source/drain terminals positioned to define a channel area in the semiconductor metal oxide layer. The etch-stop material being electrically conductive in a direction perpendicular to the plane of the blanket layer at least under the source/drain terminals to provide electrical contact between each of the source/drain terminals and the layer of semiconductor metal oxide material. The etch-stop material is also chemical robust to protect the layer of semiconductor metal oxide channel material during the etching process.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: October 23, 2018
    Assignee: CBRITE INC.
    Inventors: Gang Yu, Chan-Long Shieh, Juergen Musolf, Fatt Foong, Tian Xiao
  • Patent number: 10103175
    Abstract: A method of forming a fin-shaped structure includes the following steps. A substrate having at least a fin structure thereon is provided. A liner is formed on sidewalls of the fin structure. An oxide layer is formed between the fin structure and the substrate. The fin structure is removed until a bottom layer of the fin structure is reserved, to form a recess between the liner. A buffer epitaxial layer and an epitaxial layer are sequentially formed in the recess. A top part of the liner is removed until sidewalls of the epitaxial layer are exposed. Moreover, a fin-shaped structure formed by said method is also provided.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: October 16, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Yu-Hsiang Hung, Ssu-I Fu, Jyh-Shyang Jenq
  • Patent number: 10074595
    Abstract: An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: September 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ku-Feng Yang, Ming-Tsu Chung, Hong-Ye Shih, Jiung Wu, Chen-Yu Tsai, Hsin-Yu Chen, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 10032886
    Abstract: A semiconductor device includes a fin-type pattern including a first short side and a second short side opposed to each other, a first trench in contact with the first short side, a second trench in contact with the second short side, a first field insulating film in the first trench, the first field insulating film including a first portion and a second portion arranged sequentially from the first short side, and a height of the first portion being different from a height of the second portion, a second field insulating film in the second trench, and a first dummy gate on the first portion of the first field insulating film.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: July 24, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Yup Chung, Hyun-Jo Kim, Seong-Yul Park, Se-Wan Park, Jong-Mil Youn, Jeong-Hyo Lee, Hwa-Sung Rhee, Hee-Don Jeong, Ji-Yong Ha
  • Patent number: 10032950
    Abstract: An avalanche photodiode, and related method of manufacture and method of use thereof, that includes a first contact layer; a multiplication layer, wherein the multiplication layer includes AlInAsSb; a charge, wherein the charge layer includes AlInAsSb; an absorption, wherein the absorption layer includes AlInAsSb; a blocking layer; and a second contact layer.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: July 24, 2018
    Assignee: University of Virginia Patent Foundation
    Inventors: Joe C. Campbell, Min Ren, Madison Woodson, Yaojia Chen, Seth Bank, Scott Maddox