Patents Examined by Jesse Y Miyoshi
  • Patent number: 10032796
    Abstract: A display device includes a pixel portion in which a pixel electrode layer is arranged in a matrix, and an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen is provided corresponding to the pixel electrode layer. In the periphery of the pixel portion in this display device, a pad portion is provided to be electrically connected to a common electrode layer formed on a counter substrate through a conductive layer made of the same material as the pixel electrode layer. One objection of our invention to prevent a defect due to separation of a thin film in various kinds of display devices is realized, by providing a structure suitable for a pad portion provided in a display panel.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: July 24, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Shigeki Komori, Hideki Uochi, Rihito Wada, Yoko Chiba
  • Patent number: 10032886
    Abstract: A semiconductor device includes a fin-type pattern including a first short side and a second short side opposed to each other, a first trench in contact with the first short side, a second trench in contact with the second short side, a first field insulating film in the first trench, the first field insulating film including a first portion and a second portion arranged sequentially from the first short side, and a height of the first portion being different from a height of the second portion, a second field insulating film in the second trench, and a first dummy gate on the first portion of the first field insulating film.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: July 24, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Yup Chung, Hyun-Jo Kim, Seong-Yul Park, Se-Wan Park, Jong-Mil Youn, Jeong-Hyo Lee, Hwa-Sung Rhee, Hee-Don Jeong, Ji-Yong Ha
  • Patent number: 10032789
    Abstract: Provided is a three-dimensional semiconductor memory device including a peripheral logic structure on a semiconductor substrate to include peripheral logic circuits and a lower insulating gapfill layer, a horizontal semiconductor layer on the peripheral logic structure, stacks on the horizontal semiconductor layer, each of the stacks including a plurality of electrodes vertically stacked on the horizontal semiconductor layer, and a plurality of vertical structures passing through the stacks and connected to the horizontal semiconductor layer. The horizontal semiconductor layer may include a first semiconductor layer disposed on the lower insulating gapfill layer and co-doped with an anti-diffusion material and first conductivity type impurities of a first impurity concentration, and a second semiconductor layer disposed on the first semiconductor layer and doped with first conductivity type impurities of a second impurity concentration lower than the first impurity concentration or undoped.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: July 24, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dohyun Lee, Younghwan Son, Minyeong Song, Youngwoo Park, Jaeduk Lee
  • Patent number: 10032950
    Abstract: An avalanche photodiode, and related method of manufacture and method of use thereof, that includes a first contact layer; a multiplication layer, wherein the multiplication layer includes AlInAsSb; a charge, wherein the charge layer includes AlInAsSb; an absorption, wherein the absorption layer includes AlInAsSb; a blocking layer; and a second contact layer.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: July 24, 2018
    Assignee: University of Virginia Patent Foundation
    Inventors: Joe C. Campbell, Min Ren, Madison Woodson, Yaojia Chen, Seth Bank, Scott Maddox
  • Patent number: 10023459
    Abstract: A method and apparatus are provided to prevent or reduce stiction of a MEMS device. The MEMS device may include a protrusion extending from a surface of the MEMS device. During manufacture, the protrusion may be connected across an opening in the MEMS device to a sidewall of the substrate. Before manufacture of the MEMS device is completed, at least a portion of the protrusion connecting the MEMS device to the substrate may be removed. During operation, the protrusion may provide stiction prevention or reduction for the surface from which the first protrusion may extend. A plurality of protrusions may be formed along a plurality of surfaces for the MEMS device to prevent or reduce stiction along the corresponding surfaces. Protrusions may also be formed on devices surrounding or encapsulating the MEMS device to prevent or reduce stiction of the MEMS device to the surrounding or encapsulating devices.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: July 17, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Sung Chang, Ting-Hau Wu
  • Patent number: 10001683
    Abstract: Disclosed is a low-profile microdisplay module that comprises a package substrate, a microdisplay chip disposed over a first surface of the package substrate, and a plurality of conductive vias. The plurality of conductive vias are electrically coupled to the microdisplay chip and disposed through the package substrate to a second surface of the package substrate, the second surface being opposite and parallel to the first surface. The microdisplay module further comprises a flexible flat circuit connector coupled to the plurality of conductive vias at the second surface of the package substrate.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: June 19, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Andriy Pletenetskyy
  • Patent number: 10002876
    Abstract: A plurality of fin structures containing, from bottom to top, a non-doped semiconductor portion and a second doped semiconductor portion of a first conductivity type, extend upwards from a surface of a first doped semiconductor portion of the first conductivity type. A trapping material (e.g., an electron-trapping material) is present along a bottom portion of sidewall surfaces of each non-doped semiconductor portion and on exposed portions of each first doped semiconductor portion. Functional gate structures straddle each fin structure. Metal lines are located above each fin structure and straddle each functional gate structure. Each metal line is orientated perpendicular to each functional gate structure and has a bottommost surface that is in direct physical contact with a portion of a topmost surface of each of the second doped semiconductor portions.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: June 19, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ramachandra Divakaruni, Arvind Kumar, Carl J. Radens
  • Patent number: 9997596
    Abstract: A tunneling field-effect transistor may be provided that includes: a substrate; a source which is formed on the substrate and into which p+ type impurity ion is injected; a drain which is formed on the substrate and into which n+ type impurity ion is injected; a plurality of vertically stacked nanowire channels which are formed on the substrate; a gate insulation layer which is formed on the plurality of nanowire channels; and a gate which is formed on the gate insulation layer. As a result, it is possible to generate a higher driving current without changing the length of the gate and the area of the channel (degree of integration).
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: June 12, 2018
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Yang-Kyu Choi, Jun-Young Park
  • Patent number: 9991149
    Abstract: A transfer substrate with a compliant resin is used to bond one or more chips to a target wafer. An implant region is formed in a transfer substrate. A portion of the transfer substrate is etched to form a riser. Compliant material is applied to the transfer substrate. A chip is secured to the compliant material, wherein the chip is secured to the compliant material above the riser. The chip is bonded to a target wafer while the chip is secured to the compliant material. The transfer substrate and compliant material are removed from the chip. The transfer substrate is opaque to UV light.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: June 5, 2018
    Assignee: SKORPIOS TECHNOLOGIES, INC.
    Inventors: Damien Lambert, John Spann, Stephen Krasulick
  • Patent number: 9991343
    Abstract: The present disclosure provides an LDD-free semiconductor structure including a semiconductor layer, a gate over the semiconductor layer and a regrowth region made of semiconductor material positioned in the semiconductor layer. The regrowth region forms a source region or a drain region of the LDD-free semiconductor structure. The gate includes a gate electrode layer laterally covered by a gate spacer. The regrowth region extends towards a region beneath the gate spacer and close to a plane extending along a junction of the gate spacer and the gate electrode layer. The present disclosure also provides a method for manufacturing an LDD-free semiconductor structure. The method includes forming a gate over a semiconductor layer, removing a portion of the semiconductor layer and obtaining a recess, and forming a regrowth region over the recess.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: June 5, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chun Hsiung Tsai
  • Patent number: 9985203
    Abstract: The present disclosure provides resistive random access memory (RRAM) structures and methods of making the same. The RRAM structures include a bottom electrode having protruded step portion that allows formation of a self-aligned conductive path with a top electrode during operation. The protruded step portion may have an inclination angle of about 30 degrees to 150 degrees. Multiple RRAM structures may be formed by etching through a RRAM stack.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: May 29, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jonathan Tehan Chen, Chung-Cheng Chou, Po-Hao Lee, Kuo-Chi Tu
  • Patent number: 9985205
    Abstract: According to one embodiment, a semiconductor memory device includes first and second interconnect parts, and a second interconnect connection part. The first interconnect part includes a first core part, and a first interconnect layer. The first interconnect layer includes a first surrounding region and a first extended region. The second interconnect part includes a second core part, and a second interconnect layer. The second interconnect layer includes a second surrounding region and a second extended region. The second extended connection part overlaps a part of the first extended region in the third direction, overlaps the second core part in the first direction, and is electrically connected to the second core part. The second extended surrounding part is provided around the second extended connection part and contains a material contained in the first surrounding region.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: May 29, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yusuke Arayashiki
  • Patent number: 9972756
    Abstract: A method for producing a semiconductor light-emitting device having a substrate, an element and an encapsulating material as constituent members, includes: a first step of providing the substrate with the element; a second step of potting an uncured encapsulating material onto the substrate to cover the element; and a third step of curing the potted encapsulating material in such a manner that all of the following formulae (1), (2) and (3) are satisfied when the absorbances which a cured encapsulating material having a thickness of t [nm] has at wavelengths of 380 nm, 316 nm and 260 nm are represented by AbsA(t), AbsB(t) and AbsC(t), respectively, and the light transmittance thereof at 380 nm is represented by T(t): (1) T(1.7)?90%; (2) AbsB(t)?AbsA(t)<0.011t; and (3) AbsC(t)?AbsA(t)<0.125t.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: May 15, 2018
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Gaku Yoshikawa, Masayuki Takashima
  • Patent number: 9960172
    Abstract: Device and method for forming a device are disclosed. The method includes providing a substrate prepared with a memory cell region. At least first and second memory cells are formed on the memory cell region. Each of the memory cells is formed by forming a split gate having first and second gates. The first gate is a storage gate having a control gate over a floating gate and the second gate is a wordline. Re-oxidized layers which extend from top to bottom of the control gate are formed on sidewalls of the control gate. First source/drain (S/D) region is formed adjacent to the second gate and second S/D region is formed adjacent to the first gate. The first and second gates are coupled in series and the second S/D region is a common S/D region for adjacent first and second memory cells. An erase gate is formed over the common S/D region.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: May 1, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Jianbo Yang, Ling Wu, Sung Mun Jung
  • Patent number: 9960106
    Abstract: A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: May 1, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuo-Mao Chen, Der-Chyang Yeh, Chiung-Han Yeh
  • Patent number: 9960177
    Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell stacked structure stacked on the substrate in the cell region, a channel layer in one structure penetrating the cell stacked structure, a driving transistor formed in the peripheral region, and a plug structure coupled to the driving transistor and including a stacking structure of at least two contact plugs shorter than the channel layer, wherein each of the contact plugs is arranged at a same height as a part of the cell stacked structure.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: May 1, 2018
    Assignee: SK hynix Inc.
    Inventor: Jung Ryul Ahn
  • Patent number: 9947573
    Abstract: Lateral PiN diodes and Schottky diodes with low parasitic capacitance and variable breakdown voltage structures and methods of manufacture are disclosed. The structure includes a diode with breakdown voltage determined by a dimension between p- and n-terminals formed in an i-region above a substrate.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: April 17, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Natalie B. Feilchenfeld, Vibhor Jain, Qizhi Liu
  • Patent number: 9947662
    Abstract: A CMOS circuit comprises CMOS MOSFETs having n-type and p-type gates on the same substrate, wherein the substrate is divided into regions of n-type and p-type diffusions, and those diffusions are contained within a deeper n-type diffusion, used to junction isolate components within the deeper n-type diffusion from components outside of the deeper n-type diffusion.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: April 17, 2018
    Assignee: X-FAB SEMICONDUCTOR FOUNDRIES AG
    Inventors: Paul Ronald Stribley, John Nigel Ellis
  • Patent number: 9941129
    Abstract: A semiconductor device and a method for manufacturing the device. The method includes: depositing a first dielectric layer on a semiconductor device; forming a plurality of first trenches through the first dielectric layer; depositing an insulating fill in the plurality of first trenches; planarizing the plurality of first trenches; forming a first gate contact between the plurality of first trenches; depositing a first contact fill in the first gate contact; planarizing the first gate contact; depositing a second dielectric layer on the device; forming a plurality of second trenches through the first and second dielectric layers; depositing a conductive fill in the plurality of second trenches; planarizing the plurality of second trenches; forming a second gate contact where the second gate contact is in contact with the first gate contact; depositing a second contact fill in the second gate contact; and planarizing the second gate contact.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: April 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Josephine B. Chang, Paul Chang, Michael A. Guillorn
  • Patent number: 9941394
    Abstract: The tunnel field-effect transistor includes a drain layer, a source layer, a channel layer, a metal gate layer, and a high-k dielectric layer. The drain and source layers are of opposite conductive types. The channel layer is disposed between the drain layer and the source layer. At least one of the drain layer, the channel layer, and the source layer has a substantially constant doping concentration. The metal gate layer is disposed around the channel layer. The high-k dielectric layer is disposed between the metal gate layer and the channel layer.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: April 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chih-Tang Peng, De-Fang Chen, Hung-Ta Lin, Chien-Hsun Wang