Abstract: A display screen and an electronic device are disclosed. The display screen has a first display region and a second display region. The display screen includes an anode layer, a pixel defining layer disposed on the anode layer, a number of isolation pillars disposed on the pixel defining layer, and a driving layer group. The pixel defining layer and the isolation pillars form a sub-pixel isolation structure, and the isolation pillars, the pixel defining layer, the driving layer group, and the anode layer are disposed in the first display region and the second display region. The second display region has a vacant region corresponding to a region forming the isolation pillar and without the isolation pillar formed therein, and the pixel defining layer is provided with an opening under the vacant region.

Abstract: A thin film resistor (TFR) module is formed in an integrated circuit device. The TFR module includes a TFR element connected between first and second vertically-extending TFR side contacts. The TFR element includes a base portion extending laterally between the TFR side contacts, and first and second TFR element end flanges projecting vertically from opposing ends of the base portion. The first TFR element end flange is formed on a sidewall of the first TFR side contact, and the second TFR element end flange is formed on a sidewall of the second TFR side contact. A first TFR head contacts the first TFR side contact and a top of the first TFR element end flange, and a second TFR head contacts the second TFR side contact and a top of the second TFR element end flange, thus defining two parallel conductive paths between the TFR element and each TFR head.

Abstract: An organic light-emitting display device includes: a substrate on which a display area and a non-display area surrounding the display area are defined, the display area includes a main area and at least one protruding area, and a plurality of pixels is in the display area; a first signal line on the substrate in the main area to provide signals to the plurality of pixels; a second signal line on the substrate in the protruding area to provide signals to the plurality of pixels; a compensation line on the substrate in the non-display area and electrically connected to the second signal line; and a bridge pattern over the second signal line and the compensation line in the non-display area and electrically connecting the second signal line with the compensation line, the bridge pattern including a double-bridge structure.

Abstract: A display panel includes a substrate; an array layer, disposed on the substrate; a light-emitting structure layer, disposed on the side of the array layer away from the substrate and including a plurality of sub-pixels, including first and second sub-pixels of a same color. The display panel includes first adjustment units and second adjustment units, disposed on the light-emitting structure layer. The first adjustment units are in one-to-one correspondence with the first sub-pixels, and vertical projections of each first adjustment unit and the corresponding first sub-pixel at least partially overlap. The second adjustment units are in one-to-one correspondence with the second sub-pixels, and vertical projections of each second adjustment unit and the corresponding second sub-pixel at least partially overlap. Light beams with a same phase, after passing through a first adjustment unit and a second adjustment unit, have a non-zero phase difference.

Abstract: The object is to provide a semiconductor device that prevents a snapback operation and has excellent heat dissipation. The semiconductor device includes a semiconductor substrate, transistor portions, diode portions, a surface electrode, and external wiring. The transistor portions and the diode portions are provided in the semiconductor substrate and are arranged in one direction parallel with the surface of the semiconductor substrate. A bonding portion of the external wiring is connected to the surface electrode. The transistor portions and the diode portions are provided in a first region and a second region and alternately arranged in the one direction. A first transistor width and a first diode width in the first region are smaller than a width of the bonding portion. A second transistor width and a second diode width in the second region are larger than the width of the bonding portion.

Abstract: A sensing device includes a light-transmissible substrate, a light-transmissible electrode unit connected thereto, including multiple electrically independent electrode lines, and a light sensing unit connected to the light-transmissible substrate and the light-transmissible electrode unit. The light sensing unit includes a plurality of light sensors for sensing a light transmitted from the light-transmissible substrate. The light sensors are confined within the light-transmissible electrode unit and are electrically connectable to an outer component through the light-transmissible electrode unit.

Abstract: A display device that includes a plurality of pixels arranged in a row direction and a column direction crossing the row direction. The display device includes a first substrate including light-emitting elements each disposed in the respective pixels. A second substrate faces the first substrate. A plurality of optical patterns are disposed on the second substrate in pixel columns, respectively, and extend along the column direction. Light-blocking patterns are disposed on the second substrate. The light-blocking patterns include a main light-blocking pattern extending along pixel column boundaries and fill spaces between adjacent optical patterns, and a subsidiary light-blocking pattern disposed on the optical patterns at pixel row boundaries and having a thickness smaller than a thickness of the main light-blocking pattern.

Abstract: A display panel and a display device are provided. The display panel has a display area including a conventional display region and a translucent display region; and a non-display area. First sub-pixels, second sub-pixels and third sub-pixels are provided in the conventional display region, the first sub-pixels are arranged in a first density, and the second and third sub-pixels are arranged in a second density. Fourth sub-pixels, fifth sub-pixels and sixth sub-pixels are provided in the translucent display region, the fourth sub-pixel has a same color as the first sub-pixel, the fifth sub-pixel has a same color as the second sub-pixel, and the sixth sub-pixel has a same color as the third sub-pixel. The fourth sub-pixels are arranged in a third density equal to the first density, the fifth and sixth sub-pixels are arranged in a fourth density. The second density is greater than the fourth density.

Abstract: The present disclosure relates to a transistor device having source and drain regions within a substrate. A gate electrode is between the source and drain regions. A spacer has a lower lateral portion along an upper surface of the substrate between the gate electrode and the drain region, a vertical portion extending along a sidewall of the gate electrode, and an upper lateral portion extending from the vertical portion to an outermost sidewall directly over the gate electrode. A field plate is disposed along an upper surface and a sidewall of the spacer and is separated from the gate electrode and the substrate by the spacer. A first ILD layer overlies the substrate, the gate electrode, and the field plate. A first conductive contact has opposing outermost sidewalls intersecting a first horizontally extending surface of the field plate between the gate electrode and the drain region.

Abstract: A flexible display device including a well structure. An organic light-emitting element including a pixel electrode, an organic light-emitting layer, and a common electrode is disposed on a substrate. A bank layer is disposed on the pixel electrode, and is disposed to open at least a part of the pixel electrode. Further, at least one well structure is disposed on the bank layer. The well structure disposed on the bank layer can reduce or minimize a delamination phenomenon of an encapsulation layer which can occur due to compressive and tensile stress caused by bending of the flexible display device.

Abstract: An ESD protection element includes a semiconductor substrate, a wiring layer, and an inductor conductor. The semiconductor substrate includes a Zener diode. The inductor conductor is provided on the wiring layer and has a two-dimensional spiral shape. The inductor conductor includes a first inductor conductor and a second inductor conductor that are continuously provided from an outer peripheral end toward an inner peripheral end, and a connection conductor portion in a vicinity of a portion at which the first inductor conductor and the second inductor conductor are connected to each other. The second inductor conductor has a width smaller than a width of the first inductor conductor.

Abstract: A semiconductor structure includes: a first device; a second device contacted with the first device, wherein a chamber is formed between the first device and the second device; a first hole disposed in the second device and defined between a first end with a first circumference and a second end with a second circumference; a second hole disposed in the second device and aligned to the first hole; and a sealing object for sealing the second hole. The first end links with the chamber, and the first circumference is different from the second circumference, the second hole is defined between the second end and a third end with a third circumference, and the second circumference and the third circumference are smaller than the first circumference.

Abstract: Monolithic FETs including a majority carrier channel in a first high carrier mobility semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering a lateral channel region, a spacer of a high carrier mobility semiconductor material is overgrown, for example wrapping around a dielectric lateral spacer, to increase effective spacing between the transistor source and drain without a concomitant increase in transistor footprint. Source/drain regions couple electrically to the lateral channel region through the high-mobility semiconductor spacer, which may be substantially undoped (i.e. intrinsic). With effective channel length for a given lateral gate dimension increased, the transistor footprint for a given off-state leakage may be reduced or off-state source/drain leakage for a given transistor footprint may be reduced, for example.

Abstract: A display unit is provided with a plurality of pixels that are two-dimensionally arranged and each include an organic electroluminescence element emitting light of one of a plurality of colors. The pixels are arranged along one direction for each of light emission colors. The pixels each include a first insulating film, a second insulating film, and an organic layer. The first insulating film has openings for the respective pixels. The second insulating film extends along the arrangement direction for each of the light emission colors, in a region between pixels of different light emission colors, out of the plurality of pixels, on the first insulating film. The organic layer is formed in each of the openings, and includes a light-emitting layer. The first insulating film includes a recess that connects together the openings of pixels of the same light emission color, out of the plurality of pixels.

Abstract: A semiconductor device includes a first impurity region, a channel pattern, a second impurity region, a gate structure, a first contact pattern, a second contact pattern and a spacer. The first impurity region may be formed on a substrate. The channel pattern may protrude from an upper surface of the substrate. The second impurity region may be formed on the channel pattern. The gate structure may be formed on a sidewall of the channel pattern and the substrate adjacent to the channel pattern, and the gate structure may include a gate insulation pattern and a gate electrode. The first contact pattern may contact an upper surface of the second impurity region. The second contact pattern may contact a surface of the gate electrode. The spacer may be formed between the first and second contact patterns. The spacer may surround a portion of a sidewall of the second contact pattern, and the spacer may contact a sidewall of each of the first and second contact patterns.

Abstract: A display apparatus includes a substrate, a first pixel positioned on the substrate, a first data line which applies a first data signal to the first pixel, a second pixel positioned on the substrate and being adjacent to the first pixel, a second data line which applies a second data signal to the second pixel, and a shielding layer between the first data line and the second data line. The first data line and the second data line are parallel to each other and are disposed at different heights, and the shielding layer includes a metallic layer.

Abstract: A method of manufacturing an imaging apparatus includes: preparing a substrate comprising a wafer and a silicon layer arranged on the wafer, the wafer including a first semiconductor region made of single crystal silicon with an oxygen concentration not less than 2×1016 atoms/cm3 and not greater than 4×1017 atoms/cm3, the silicon layer including a second semiconductor region made of single crystal silicon with an oxygen concentration lower than the oxygen concentration in the first semiconductor region; annealing the substrate in an atmosphere containing oxygen and setting the oxygen concentration in the second semiconductor region within the range not less than 2×1016 atoms/cm3 and not greater than 4×1017 atoms/cm3; and forming a photoelectric conversion element in the second semiconductor region after the annealing.

Abstract: A semiconductor device may include a source layer, a stack structure, a channel layer, a slit, and a source pick-up line. The source layer may include at least one groove in an upper surface thereof. The stack structure may be formed over the source layer. The channel layer may pass through the stack structure. The channel layer may be in contact with the source layer. The slit may pass through the stack structure. The slit may expose the groove of the source layer therethrough. The source pick-up line may be formed in the slit and the groove. The source pick-up line may be contacted with the source layer.

Abstract: Interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the interconnects are disclosed herein. An exemplary interconnect is disposed in an insulating layer. The interconnect has a metal contact, a contact isolation layer surrounding sidewalls of the metal contact, and an air gap disposed between the contact isolation layer and the insulating layer. An air gap seal for the air gap has a first portion disposed over a top surface of the contact isolation layer, but not disposed on a top surface of the insulating layer, and a second portion disposed between the contact isolation layer and the insulating layer, such that the second portion surrounds a top portion of sidewalls of the metal contact. The air gap seal may include amorphous silicon and/or silicon oxide. The contact isolation layer may include silicon nitride. The insulating layer may include silicon oxide.

Abstract: The present application provides a flexible display apparatus. The flexible display apparatus includes a flexible display panel; and a hardness-enhancing layer on the flexible display panel, the hardness-enhancing layer for enhancing surface hardness and mechanical strength of the flexible display panel. The hardness-enhancing layer includes an inorganic material sublayer and a composite material sublayer, the composite material sublayer including a polymer matrix and an inorganic material dispersed in the polymer matrix.