Patents Examined by Jesse Y Miyoshi
  • Patent number: 9768079
    Abstract: A method for forming semiconductor devices includes forming a highly doped region. A stack of alternating layers is formed on the substrate. The stack is patterned to form nanosheet structures. A dummy gate structure is formed over and between the nanosheet structures. An interlevel dielectric layer is formed. The dummy gate structures are removed. SG regions are blocked, and top sheets are removed from the nanosheet structures along the dummy gate trench. A bottommost sheet is released and forms a channel for a field effect transistor device by etching away the highly doped region under the nanosheet structure and layers in contact with the bottommost sheet. A gate structure is formed in and over the dummy gate trench wherein the bottommost sheet forms a device channel for the EG device.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: September 19, 2017
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Terence B. Hook, Junli Wang
  • Patent number: 9761482
    Abstract: A process of making a semiconductor structure. The process includes forming a wiring line; forming a reliability enhancement material on the wiring line; forming an interlayer dielectric (ILD) layer on the wiring line; forming a via opening through the ILD layer and reliability enhancement material to expose a surface of the wiring line; and filling the via opening with a metal to form a metal-filled via in contact with the wiring line wherein the reliability enhancement material is in direct contact with the metal-filled via; wherein the reliability enhancement material causes a compressive stress on the metal-filled via where it contacts the wiring line. Another embodiment includes the metal-filled via being an iso-via so that there is only one metal-filled via per wiring line.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: September 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Baozhen Li, Xiao H. Liu, Kirk D. Peterson
  • Patent number: 9755048
    Abstract: A patterned structure of a semiconductor device includes a substrate, a first feature and a second feature. The first feature and the second feature are disposed on the substrate, and either of which includes a vertical segment and a horizontal segment. There is a distance between the vertical segment of the first feature and the vertical segment of the second feature, and the distance is less than the minimum exposure limits of an exposure apparatus.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: September 5, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Rai-Min Huang, I-Ming Tseng, Tong-Jyun Huang, Kuan-Hsien Li
  • Patent number: 9755024
    Abstract: Functionalized films are provided comprising a film of ZnO or ZnO alloy disposed over a supporting substrate and a layer of organic molecules comprising terminal carboxylic acid linkage groups, wherein the organic molecules are bound to a surface of the film of ZnO or ZnO alloy via the terminal carboxylic acid linkage groups. Thin film transistors comprising the functionalized films are also provided. The functionalized films may be formed using polycrystalline ZnO and saturated fatty acids, such as stearic acid.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: September 5, 2017
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Paul G. Evans, Josef W. Spalenka
  • Patent number: 9753590
    Abstract: Disclosed is a display device that may, for example, include a gate line that is provided in a first direction on a backplane and delivers a gate signal; a data line that is provided in a second direction on the backplane and delivers a data signal; a Thin Film Transistor (TFT) in each pixel defined by a crossing between the gate line and the data line; a first electrode spaced apart from one of a source electrode and a drain electrode of the TFT; a second electrode that is provided on a layer different from that on which the first electrode is provided; a TFT passivation layer that is provided on the TFT and has a first contact hole; a first connection pattern that connects one of the source electrode and the drain electrode to the first electrode through the first contact hole; and a second connection pattern that delivers a touch driving signal to the second electrode and is formed of a material substantially identical to that of the first connection pattern.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: September 5, 2017
    Assignee: LG Display Co., Ltd.
    Inventors: Sanghyuk Won, MinJoo Kim
  • Patent number: 9755169
    Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes: first and second electrodes spaced from each other; at least one nano crystal layer disposed between the first and second electrodes; and first and second material layers respectively disposed between the first and second electrodes and the nano crystal layer and having a bistable conductive property, wherein the first and second material layers are formed asymmetrical to each other.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: September 5, 2017
    Assignee: IUCF-HYU
    Inventors: Jea Gun Park, Sung Ho Seo, Woo Sik Nam, Jong Sun Lee
  • Patent number: 9748286
    Abstract: A method for manufacturing a thin film transistor substrate, the method can include a first mask process for forming a gate electrode on a substrate; a step for forming a gate insulating layer covering the gate electrode; a second mask process for forming a source electrode overlapping with one side of the gate electrode, and a drain electrode overlapping with other side of the gate electrode and being apart from the source electrode, on the gate insulating layer; and a third mask process for forming an oxide semiconductor layer extending from the source electrode to the drain electrode, and an etch stopper having the same shape and size with the oxide semiconductor layer on the oxide semiconductor layer.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: August 29, 2017
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Sungkeun Lee, Yongtae Song, Imkuk Kang, Sungjun Yun, Woocheol Jeong
  • Patent number: 9741899
    Abstract: An interface including roughness components for improving the propagation of radiation through the interface is provided. The interface includes a first profiled surface of a first layer comprising a set of large roughness components providing a first variation of the first profiled surface having a first characteristic scale and a second profiled surface of a second layer comprising a set of small roughness components providing a second variation of the second profiled surface having a second characteristic scale. The first characteristic scale is approximately an order of magnitude larger than the second characteristic scale. The surfaces can be bonded together using a bonding material, and a filler material also can be present in the interface.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: August 22, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 9741675
    Abstract: The present disclosure relates to bump structures and a semiconductor device and semiconductor device package having the same. The semiconductor device includes a body, at least one conductive metal pad and at least one metal pillar. The body includes a first surface. The at least one conductive metal pad is disposed on the first surface. Each metal pillar is formed on a corresponding conductive metal pad. Each metal pillar has a concave side wall and a convex side wall opposite the first concave side wall, and the concave side wall and the convex side wall are orthogonal to the corresponding conductive metal pad.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: August 22, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Dao-Long Chen, Ping-Feng Yang, Chang-Chi Lee, Chien-Fan Chen
  • Patent number: 9735136
    Abstract: Several embodiments of microelectronic configurations with logic components and associated methods of manufacturing are disclosed herein. In one embodiment, the configuration includes a substrate with a recess, a first die carried by the substrate wherein the die substantially covers the recess, and a logic component carried by the die in a location exposed by the recess. The logic component can be substantially coplanar with the substrate. The die is electrically connected to a terminal on a one side of the substrate, and the logic component is electrically connected to a terminal on an opposite side of the substrate.
    Type: Grant
    Filed: March 9, 2009
    Date of Patent: August 15, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Paul Silvestri, Jonathon G. Greenwood
  • Patent number: 9735359
    Abstract: A method of forming a memory cell material comprises forming a first portion of a dielectric material over a substrate by atomic layer deposition. Discrete conductive particles are formed on the first portion of the dielectric material by atomic layer deposition. A second portion of the dielectric material is formed on and between the discrete conductive particles by atomic layer deposition. A memory cell material, a method of forming a semiconductor device structure, and a semiconductor device structure are also described.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: August 15, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, John A. Smythe
  • Patent number: 9728489
    Abstract: Inter-substrate coupling and alignment using liquid droplets can include electrical and plasmon modalities. For example, a set of droplets can be placed on a bottom substrate. A top substrate can be placed upon the droplets, which uses the droplets to align the substrates. Using the droplets in a capacitive or plasmon coupling modality, information or power can be transferred between the substrates using the droplets.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: August 8, 2017
    Assignee: ELWHA LLC
    Inventors: William David Duncan, Roderick A. Hyde, Jordin T. Kare, Thomas M. McWilliams, Thomas Allan Weaver, Lowell L. Wood, Jr.
  • Patent number: 9722144
    Abstract: Contrary to conventional wisdom, which holds that light-emitting diodes (LEDs) should be cooled to increase efficiency, the LEDs disclosed herein are heated to increase efficiency. Heating an LED operating at low forward bias voltage (e.g., V<kBT/q) can be accomplished by injecting phonons generated by non-radiative recombination back into the LED's semiconductor lattice. This raises the temperature of the LED's active rejection, resulting in thermally assisted injection of holes and carriers into the LED's active region. This phonon recycling or thermo-electric pumping process can be promoted by heating the LED with an external source (e.g., exhaust gases or waste heat from other electrical components). It can also be achieved via internal heat generation, e.g., by thermally insulating the LED's diode structure to prevent (rather than promote) heat dissipation. In other words, trapping heat generated by the LED within the LED increases LED efficiency under certain bias conditions.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: August 1, 2017
    Assignee: Massachusetts Institute of Technology
    Inventors: Parthiban Santhanam, Dodd Joseph Gray, Rajeev Jagga Ram
  • Patent number: 9714914
    Abstract: The present disclosure relates to an integrated chip having an integrated bio-sensor with a sensing well having one or more sensing well spacers that reduce a size of the sensing well after its formation. In some embodiments, the integrated bio-sensor has a sensing device disposed within a semiconductor substrate. A dielectric structure is disposed onto a first side of the semiconductor substrate. The dielectric structure has an opening with a first width, which is exposed to an ambient environment and that overlies the sensing device. One or more sensing well spacers are arranged on sidewalls of the opening. The one or more sensing well spacers expose a bottom surface of the opening to define a sensing well having a second width that is smaller than the first width.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: July 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lee-Chuan Tseng, Che-Ming Chang, Chung-Yen Chou, Yuan-Chih Hsieh
  • Patent number: 9713258
    Abstract: An electrical circuit device that includes a circuit board with an integrated circuit chip in a cavity that extends from a surface of the circuit board to an embedded conductor, and an electrical connection between the integrated circuit chip and the embedded conductor.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: July 18, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Young Hoon Kwark
  • Patent number: 9696602
    Abstract: A method for manufacturing a liquid crystal display includes: forming a first passivation layer and an organic layer, forming an edge of an inclined portion of the organic layer by partially removing the organic layer at a location where a first drain contact hole that exposes a drain electrode of a thin film transistor is formed, forming a second passivation layer including a third drain contact hole exposing the drain electrode, a first electrode including a second drain contact hole exposing the drain electrode, and the first drain contact hole through an etching process using one etching mask, and forming a second electrode on the second passivation layer. The first drain contact hole, the second drain contact hole, and the third drain contact hole overlap with each other, and a size of the second drain contact hole is greater than a size of the third drain contact hole.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: July 4, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang Bae Park, Young Woon Kho, Yu Jun Kim, Tae Ho Kim, Jong Kyun Park, Ji Young Jeong
  • Patent number: 9698319
    Abstract: A light emitting diode (LED) package according to an exemplary embodiment of the present invention includes a base including a first lead terminal and a second lead terminal, an LED chip disposed on the base, a housing disposed on the base, the housing having a cavity in which the LED chip is disposed, and an encapsulation member having a side surface contacting the housing. The first lead terminal and the second lead terminal each have a first surface and a second surface opposite the first surface, and have an unbent form, respectively. The second surface is exposed to the outside of the LED package.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: July 4, 2017
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventors: Chung Hoon Lee, Yoon Hee Kim, Byung Yeol Park, Bang Hyun Kim, Eun Jung Seo, Hyouk Won Kwon
  • Patent number: 9691664
    Abstract: A method of forming a thick oxide layer over fins for EG devices and a thinner oxide layer over fins for SG devices on the same substrate and the resulting device are provided. Embodiments include forming a first set of fins over a first portion of a Si substrate; forming a second set of fins over a second portion of the Si substrate spaced from the first portion; forming an iRAD SiO2 layer over the first and second sets of fins; forming a polysilicon layer over the iRAD SiO2 layer over the first set of fins; forming a radical SiO2 layer over the iRAD SiO2 layer over the second set of fins and over the polysilicon layer; forming a mask over the radical SiO2 layer over the second set of fins; removing the polysilicon layer; and removing the mask and the iRAD SiO2 layer from the first set of fins.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: June 27, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Min Gyu Sung, Chanro Park, Hoon Kim, Ruilong Xie
  • Patent number: 9679806
    Abstract: An embodiment of the invention may include a semiconductor structure, and method of forming the semiconductor structure. The semiconductor structure may include a first set of pillars located on a first substrate. The semiconductor structure may include a second set of pillars located on a second substrate. The semiconductor structure may include a joining layer connecting the first pillar to the second pillar. The semiconductor structure may include an underfill layer located between the first and second substrate.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: June 13, 2017
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter
  • Patent number: 9673218
    Abstract: A semiconductor device according to an embodiment of the invention includes a pipe channel layer including a first portion and a second portion protruding from the first portion, first channel pillars protruding from the second portion of the pipe channel layer, and second channel pillars protruding from the first portion of the pipe channel layer.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: June 6, 2017
    Assignee: SK hynix Inc.
    Inventors: Hyun Ho Lee, Ji Hye Shin