Patents Examined by Jessica Stultz
  • Patent number: 9496292
    Abstract: The present invention provides a display device having: gate electrodes formed on a transparent substrate; a gate insulating film for covering the gate electrodes; an oxide semiconductor formed on the gate insulating film; drain electrodes and source electrodes formed at a distance from each other with channel regions of the oxide semiconductor in between; an interlayer capacitor film for covering the drain electrodes and source electrodes; common electrodes formed on top of the interlayer capacitor film; and pixel electrodes formed so as to face the common electrodes, and wherein an etching stopper layer for covering the channel regions is formed between the oxide semiconductor and the drain electrodes and source electrodes, the drain electrodes are a multilayer film where a transparent conductive film and a metal film are layered on top of each other, and the drain electrodes and source electrodes make direct contact with the oxide semiconductor.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: November 15, 2016
    Assignee: Japan Display Inc.
    Inventors: Hidekazu Miyake, Norihiro Uemura, Takeshi Noda, Isao Suzumura, Toshiki Kaneko
  • Patent number: 9490443
    Abstract: A light emitting display device and a method for fabricating the same. The light emitting display device includes a substrate, a first electrode arranged on the substrate, a first insulating film arranged on the substrate and including a first opening that exposes a portion of the first electrode, a second insulating film arranged on the first insulating film and including a second opening that exposes the first opening, a light emitting layer including a light emitting material arranged on the exposed portion of first electrode while also being in contact with the first insulating film and a second electrode arranged on the light emitting layer, wherein a difference in wetting between the first electrode and the first insulating film with respect to the light emitting material is lower than a difference in wetting between the first electrode and the second insulating film with respect to the light emitting material.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: November 8, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sung Joong Joo, You Min Cha
  • Patent number: 9484453
    Abstract: Aspects of the present disclosure describe a high density trench-based power. The active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. A lightly doped sub-body layer may be formed below a body region between two or more adjacent active device structures of the plurality. The sub-body layer extends from a depth of the upper portion of the gate oxide to a depth of the lower portion of the gate oxide It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: November 1, 2016
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Hamza Yilmaz, Madhur Bobde, Hong Chang, Yeeheng Lee, Daniel Calafut, Jongoh Kim, Sik Lui, John Chen
  • Patent number: 9478672
    Abstract: A diode is provided which includes at least one diode element which has a plurality of N-type regions and a plurality of P-type regions, the N-type regions and the P-type regions being alternately arranged in series to form PN junctions, and an insulated substrate which has electric insulation. The N-type regions and the P-type regions are formed on the insulated substrate.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: October 25, 2016
    Assignee: DENSO CORPORATION
    Inventor: Takeshi Fukazawa
  • Patent number: 9463333
    Abstract: The invention relates to a skin treatment device, a lamp for use in such a skin treatment device, and its use. The skin treatment device according to the invention uses a combination of tanning-effective and/or anti-acne effective amounts of blue light in the spectral range from 400-440 nm in addition to the UV-light known in the art. An important advantage is that a lower UV dose can be used, leading to lower health risks, while the exposure times can be kept within acceptable limits, without compromising the skin treatment result.
    Type: Grant
    Filed: September 17, 2007
    Date of Patent: October 11, 2016
    Assignee: Koninklijke Philips N.V.
    Inventors: Giovanna Wagenaar Cacciola, Yvonne Elizabeth Dietzenbacher-Jansen, Adriaantje Pieternella Mouws-Van Rossum
  • Patent number: 9455191
    Abstract: In one embodiment there is disclosed a method for manufacturing an integrated circuit in a semiconductor substrate including through vias and a coplanar line, including the steps of: forming active components and a set of front metallization levels; simultaneously etching from the rear surface of the substrate a through via hole and a trench crossing the substrate through at least 50% of its height; coating with a conductive material the walls and the bottom of the hole and of the trench; and filling the hole and the trench with an insulating filling material; and forming a coplanar line extending on the rear surface of the substrate, in front of the trench and parallel thereto, so that the lateral conductors of the coplanar line are electrically connected to the conductive material coating the walls of the trench.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: September 27, 2016
    Assignee: STMicroelectronics SA
    Inventors: Sylvain Joblot, Pierre Bar
  • Patent number: 9437440
    Abstract: A method for producing a semiconductor device is provided. The method includes: forming in a semiconductor substrate a plurality of semiconductor mesas extending to an upper side so that adjacent semiconductor mesas are spaced apart from each other by one of a substantially empty trench and a trench substantially filled with a sacrificial layer selectively etchable with respect to the semiconductor mesas; forming a support structure mechanically connecting the semiconductor mesas spaced apart from each other by one of the substantially empty trench and the trench substantially filled with the sacrificial layer; and processing the semiconductor substrate from the upper side while the semiconductor mesas are mechanically connected via the support structure.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: September 6, 2016
    Assignee: Infineon Technologies Dresden GmbH
    Inventors: Kurt Sorschag, Daniel Sarlette, Felix Braun, Marcel Heller, Dieter Kaiser, Ingo Meusel, Marko Lemke, Anton Mauder, Helmut Strack
  • Patent number: 9437592
    Abstract: A switching device according to the present invention is a switching device for switching a load by on-off control of voltage, and includes an SiC semiconductor layer where a current path is formed by on-control of the voltage, a first electrode arranged to be in contact with the SiC semiconductor layer, and a second electrode arranged to be in contact with the SiC semiconductor layer for conducting with the first electrode due to the formation of the current path, while the first electrode has a variable resistance portion made of a material whose resistance value increases under a prescribed high-temperature condition for limiting current density of overcurrent to not more than a prescribed value when the overcurrent flows to the current path.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: September 6, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Yuki Nakano, Hiroyuki Sakairi
  • Patent number: 9437732
    Abstract: A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate and extends in a first direction with a first insulating film around the fin-shaped semiconductor layer. A pillar-shaped semiconductor layer resides on the fin-shaped semiconductor layer. A width of the bottom of the pillar-shaped semiconductor layer, perpendicular to the first direction is equal to a width of the top of the fin-shaped semiconductor layer perpendicular to the first direction. A gate insulating film is around the pillar-shaped semiconductor layer and a metal gate electrode is around the gate insulating film. A metal gate line extends in a second direction perpendicular to the first direction of the fin-shaped semiconductor layer and is connected to the metal gate electrode.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: September 6, 2016
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9431583
    Abstract: A light emitting device is provide comprising a light emitting diode (LED) chip having a first main surface and a second main surface opposing the first main surface, and one or more side surfaces extending between the first main surface and second main surface. A plurality of electrodes is disposed on the first main surface. A wavelength conversion film is disposed on the second main surface. A mark is formed in the wavelength conversion film. The mark contains orientation information of the light emitting device, thereby enabling the light emitting device to be properly oriented on a receiving substrate.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: August 30, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae Gyu Kim, Tai Oh Chung, Hyoung Cheol Cho, Min Soo Han
  • Patent number: 9431792
    Abstract: A method and apparatus for active voltage regulation in optical modules utilize a voltage regulator to change the supply voltage provided to laser diode driver and receiver electronics to optimize module performance over temperature. The ambient temperature of the module is monitored. The outputs of the voltage regulator are controlled to provide voltages that are optimized with respect to temperature for the integrated circuits in the optical module. This control is implemented via a temperature sensitive feedback or a control input from a microcontroller with a temperature monitor input. The supply voltage is optimized to minimize the voltage required to achieve acceptable performance at a given temperature. Minimizing the supply voltage lengthens the lifetime of the integrated circuit and the optical module. The voltage regulator provides higher than standard supply voltages to a laser diode driver to compensate for higher laser voltage at low temperatures.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: August 30, 2016
    Assignee: ZEPHYR PHOTONICS INC.
    Inventor: Duane Louderback
  • Patent number: 9425267
    Abstract: Transistors and methods of fabricating are described herein. These transistors include a field plate (108) and a charged dielectric layer (106) overlapping at least a portion of a gate electrode (102). The field plate (108) and charged dielectric layer (106) provide the ability to modulate the electric field or capacitance in the transistor. For example, the charged dielectric layer (106) provides the ability to control the capacitance between the gate electrode (102) and field plate (108). Modulating such capacitances or the electric field in transistors can facilitate improved performance. For example, controlling gate electrode (102) to field plate (108) capacitance can be used to improve device linearity and/or breakdown voltage. Such control over gate electrode (102) to field plate (108) capacitance or electric fields provides for high speed and/or high voltage transistor operation.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 23, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jenn Hwa Huang, James A. Teplik
  • Patent number: 9425583
    Abstract: An aluminium gallium indium phosphide (AlGaInP)-based semiconductor laser device is provided. On a main surface of a semiconductor substrate formed of n-type GaAs (gallium arsenide), from the bottom layer, an n-type buffer layer, an n-type cladding layer formed of an AlGaInP-based semiconductor containing silicon (Si) as a dopant, an active layer, a p-type cladding layer formed of an AlGaInP-based semiconductor containing magnesium (Mg) or zinc (Zn) as a dopant, an etching stopper layer, and a p-type contact layer are formed. Here, when an Al composition ratio x of the AlGaInP-based semiconductor is taken as a composition ratio of Al and Ga defined as (AlxGa1?x)0.5In0.5P, a composition of the n-type cladding layer is expressed as (AlxnGa1?xn)0.5In0.5P (0.9<xn<1) and a composition of the p-type cladding layer is expressed as (AlxpGa1?xp)0.5In0.5P (0.9<xp?1), and xn and xp satisfy a relationship of xn<xp.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: August 23, 2016
    Assignee: USHIO OPTO SEMICONDUCTORS, INC.
    Inventors: Masato Hagimoto, Haruki Fukai, Tsutomu Kiyosumi, Shinji Sasaki, Satoshi Kawanaka
  • Patent number: 9418902
    Abstract: A method of isolating a semiconductor fin from an underlying substrate including forming a masking layer around a base portion of the fin, forming spacers on a top portion of the fin above the masking layer, removing the masking layer to expose the base portion of the fin, and converting the base portion of the fin to an isolation region that electrically isolates the fin from the substrate. The base portion of the fin may be converted to an isolation region by oxidizing the base portion of the fin, using for example a thermal oxidation process. While converting the base portion of the fin to an isolation region, the spacers prevent the top portion of the fin from also being converted.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: August 16, 2016
    Assignee: Globalfoundries Inc.
    Inventors: Kangguo Cheng, Shom S. Ponoth, Balasubramanian Pranatharthiharan, Theodorus E. Standaert, Tenko Yamashita
  • Patent number: 9414470
    Abstract: A hand held, home use, device for treatment of skin, comprising: a housing exhibiting an opening therein and forming an air cavity when the opening is placed in contact with the skin; an incandescent type bulb secured within the housing and arranged to irradiate the skin with infra-red radiation and heat air within the formed air cavity, the incandescent type bulb exhibiting a filament; and a control and driving circuitry in electrical communication with the incandescent type bulb and operative to output a train of pulses exhibiting an on time when current is driven through the filament and an off time when current is not driven through the filament, the off time greater than or equal to the on time, the off time being of a duration such that the infra-red radiation irradiating the skin falls, during the off time, to no less than 25% of its maximum value.
    Type: Grant
    Filed: October 5, 2008
    Date of Patent: August 9, 2016
    Assignee: RADIANCY INC.
    Inventors: Philip Solomon, Dolev Rafaeli
  • Patent number: 9407068
    Abstract: A broadband, integrated quantum cascade laser is disclosed, comprising ridge waveguide quantum cascade lasers formed by applying standard semiconductor process techniques to a monolithic structure of alternating layers of claddings and active region layers. The resulting ridge waveguide quantum cascade lasers may be individually controlled by independent voltage potentials, resulting in control of the overall spectrum of the integrated quantum cascade laser source. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: August 2, 2016
    Assignee: California Institute of Technology
    Inventors: Kamjou Mansour, Alexander Soibel
  • Patent number: 9407066
    Abstract: III-V lasers integrated with silicon photonic circuits and methods for making the same include a three-layer semiconductor stack formed from III-V semiconductors on a substrate, where a middle layer has a lower bandgap than a top layer and a bottom layer; a mirror region monolithically formed at a first end of the stack, configured to reflect emitted light in the direction of the stack; and a waveguide region monolithically formed at a second end of the stack, configured to transmit emitted light.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: August 2, 2016
    Assignee: GlobalFoundries, Inc.
    Inventors: Cheng-Wei Cheng, Frank R. Libsch, Tak H. Ning, Uzma Rana, Kuen-Ting Shiu
  • Patent number: 9407058
    Abstract: In a method of stabilizing pump energy, a gain medium is provided having an absorption coefficient that varies with wavelength. An absorption coefficient curve of the absorption coefficient or a range of wavelengths comprises peaks and valleys. Pump energy is generated at an operating wavelength within one of the valleys, at which the absorption coefficient is approximately at a minimum. The pump energy is transmitted through the gain medium. A portion of the pump energy is absorbed with the gain medium and laser light is emitted from the gain medium responsive to the absorbed pump energy. The non-absorbed pump energy (feedback pump energy) is fed back to the pump module. The operating wavelength of the pump energy is stabilized using the feedback pump energy.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: August 2, 2016
    Assignee: Boston Scientific Scimed, Inc.
    Inventors: Edward D. Reed, Raymond Adam Nemeyer
  • Patent number: 9385509
    Abstract: A monolithic tunable mid-infrared laser has a wavelength range within the range of 3-14 ?m and comprises a heterogeneous quantum cascade active region together with at least a first integrated grating. The heterogeneous quantum cascade active region comprises at least one stack, the stack comprising two, desirably at least three differing stages. Methods of operating and calibrating the laser are also disclosed.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: July 5, 2016
    Assignee: Thorlabs Quantum Electronics, Inc.
    Inventors: Catherine Genevieve Caneau, Lawrence Charles Hughes, Jr., Feng Xie, Chung-En Zah
  • Patent number: 9385218
    Abstract: A semiconductor structure is provided that includes a fin structure of, from bottom to top, a semiconductor punch through stop (PTS) doping fin portion, a dielectric material fin portion, and a topmost semiconductor fin portion that is present on a wider semiconductor fin base. A functional gate structure straddles the semiconductor fin structure. Portions of the wider semiconductor fin base that are not located directly beneath the fin structure of the present application and that are not covered by the functional gate structure can be used as an area for epitaxial growth of source/drain structures. The wide semiconductor fin base improves source/drain epitaxy for better dopant incorporation and strain enhancement.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: July 5, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Alexander Reznicek