Abstract: A semiconductor structure is provided that includes a fin structure of, from bottom to top, a semiconductor punch through stop (PTS) doping fin portion, a dielectric material fin portion, and a topmost semiconductor fin portion that is present on a wider semiconductor fin base. A functional gate structure straddles the semiconductor fin structure. Portions of the wider semiconductor fin base that are not located directly beneath the fin structure of the present application and that are not covered by the functional gate structure can be used as an area for epitaxial growth of source/drain structures. The wide semiconductor fin base improves source/drain epitaxy for better dopant incorporation and strain enhancement.

Abstract: A method for planarizing a semiconductor device is provided. The method includes steps hereinafter. A substrate is provided with a first dielectric layer covering at least one electrode structure formed thereon. A chemical-mechanical polishing (CMP) process is performed on the first dielectric layer until the at least one electrode structure is exposed. A second dielectric layer is deposited covering the at least one electrode structure and the first dielectric layer. An etching-back process is performed on the second dielectric layer until the at least one electrode structure is exposed.

Abstract: A radiation-emitting component is specified, having a metallic carrier body (1), which comprises at least two connection locations (1a, 1b) for making electrical contact with the component, a laser diode chip (2), which is fixed to the metallic carrier body (1) and is electrically conductively connected to the at least two connection locations (1a, 1b), a housing (3), which surrounds the metallic carrier body (1) in places, wherein the housing (3) is formed with a plastic, the connection locations (1a, 1b) extend in each case at least in places along a bottom face (3a) and a side face (3b) of the housing (3), said side face running transversely with respect to the bottom face, and the component is surface-mountable by means of the connection locations (1a, 1b) in such a way that the bottom face (3a) or the side face (3b) forms a mounting face of the component.

Abstract: A circularly polarizing plate includes a polarizing film, a first optically anisotropic layer, and a second optically anisotropic layer in this order, in which the first optically anisotropic layer contains a twisted aligned liquid crystal compound of which a helical axis is a thickness direction thereof, a helix angle of the liquid crystal compound is 28.6±10°, an absorption axis of the polarizing film and an in-plane slow axis of the second optically anisotropic layer are parallel or orthogonal to each other, ?nd and ReB(550) respectively fall in predetermined value ranges. The circularly polarizing plate can sufficiently suppress the mixing of black with other colors in a front direction when being stuck on a display apparatus. A retardation plate used for the circularly polarizing plate and an organic EL display apparatus that have the circularly polarizing plate are also provided.

Abstract: A method is provided for manufacturing a semiconductor device with a metal film resistor structure. The method includes providing an insulation layer on the semiconductor device. A lower copper interconnect is formed in the insulation layer. The method also includes forming a cap layer on the insulation layer and the lower copper interconnect and etching the cap layer based on a single photolithography mask to form a window exposing portion of the lower copper interconnect and portion of the insulation layer. Further, the method includes forming a metal film layer on the cap layer and inside the window such that exposed portion of the lower copper interconnect is connected with part of the metal film layer within the window. The method also includes performing a chemical mechanical polishing (CMP) process to form a metal film resistor based on the metal film layer. The metal film resistor is connected with the portion of the lower copper interconnect.

Abstract: To provide a semiconductor device capable of suppressing a reduction in breakdown voltage by suppressing a change in dimensions of a double RESURF structure, and a method of manufacturing the same. In the semiconductor device, an upper RESURF region is formed so as to contact with a first buried region on a side of the one main surface within a semiconductor substrate. The semiconductor substrate has a field oxide formed so as to reach the upper RESURF region on the one main surface. The semiconductor substrate includes a second conductivity type body region formed so as to contact with the upper RESURF region on a side of the one main surface and so as to neighbor the field oxide within the semiconductor substrate.

Abstract: A surface emitting laser in which a plurality of nitride semiconductor layers including a lower reflector, a plurality of active layers causing a gain by current injection, and an upper reflector are provided on a substrate, includes an n-type spacer layer formed between the lower reflector and an active layer closest to the lower reflector in the plurality of active layers, a p-type spacer layer formed between the upper reflector and an active layer closest to the upper reflector in the plurality of active layers, and an intermediate layer arranged between the plurality of active layers. The intermediate layer is configured from an Mg-doped layer including at least Mg, and a nitride semiconductor layer including In, and the Mg-doped layer and the nitride semiconductor layer including In are provided in that order from a side of the substrate.

Abstract: A quantum cascade laser includes a substrate having first, second, third, and fourth regions; a stacked semiconductor layer including n-type lower and upper conductive layers, a core layer having a mesa structure, and a cladding layer; first and second buried layers disposed on side surfaces of the core layer and above the substrate; a first electrode disposed on the upper conductive layer above the first region; and a second electrode disposed on the lower conductive layer above the fourth region. The core layer is disposed on the lower conductive layer above the second region. The upper conductive layer is disposed on the first buried layer and the core layer. The cladding layer is disposed on the upper conductive layer above the second region. The substrate and the cladding layer are formed of an undoped or semi-insulating semiconductor. The first and second buried layers are formed of a semi-insulating semiconductor.

Abstract: A vertical-cavity surface-emitting laser diode includes: a first resonator that has a plurality of semiconductor layers comprising a first current narrowing structure having a first conductive region and a first non-conductor region; a first electrode that supplies electric power to drive the first resonator; a second resonator that has a plurality of semiconductor layers comprising a second current narrowing structure having a second conductive region and a second non-conductive region and that is formed side by side with the first resonator, the second current narrowing structure being formed in same current narrowing layer as the layer where the first current narrowing structure is formed; and a coupling portion as defined herein; and an equivalent refractive index of the coupling portion is smaller than an equivalent refractive index of each of the first resonator and the second resonator.

Abstract: An optical pumping structure for lasers includes: an active medium in the form of a cylindrical rod with a circular cross-section, said rod being inserted at its ends into two rings made of a thermally conductive material; at least three stacks of pumping diode strips arranged in the form of a star around the rod; and a support temperature-regulated by a Peltier-effect module. The rings are in contact with the support, and a stack of diodes, called bottom stack, being situated between the rod and the support, and the structure comprises, for each other stack, a thermal conduction block forming a support for said stack, these blocks being mounted on the cooled support and not being in contact with one another or with the rings.

Abstract: It is the object of the present invention to specify a light source with high efficiency and high eye safety at the same time. For this purpose, the active layer (10), the first cladding layer (14), the first waveguide layer (12), the second waveguide layer (16), and the second cladding layer (18) should be designed such that 0.01 ?m?dwL?1.0 ?m and ?n?0.04, where dwL is the sum total of the layer thickness of the first waveguide layer (12), the layer thickness of the active layer (10), and the layer thickness of the second waveguide layer (16) and ?n is a maximum of the refractive index difference between the first cladding layer (14) and the first waveguide layer (12) and the refractive index difference between the second waveguide layer (16) and the second cladding layer (18).

Abstract: Embodiments for driving a laser diode includes generating a bias current having a duty cycle that is less than 100%. The current level of the bias current is insufficient to turn on the laser diode. A drive current is generated and combined with the bias current to turn on the laser diode almost instantly.

Abstract: A field effect transistor having a diamond gate electrode and a process for forming the same. In some embodiments, the device is an AlGaN/GaN high-electron-mobility transistor (HEMT). The diamond gate electrode is formed so that it directly contacts the barrier layer. In some embodiments, the diamond gate electrode is formed from boron-doped nanocrystalline diamond (NCD), while in other embodiments, the diamond gate electrode is formed from single crystal diamond.

Abstract: The present invention relates to a wavelength-tunable laser apparatus which can measure a wavelength in a wavelength-tunable laser diode package structure for dense wavelength division multiplexing (DWDM) having a transistor outline (TO) type appearance.

Abstract: A plasmonic laser device has resonant nanocavities filled with a gain medium containing an organic dye. The resonant plasmon frequencies of the nanocavities are tuned to align with both the absorption and emission spectra of the dye. Variables in the system include the nature of the dye and the wavelength of its absorption and emission, the wavelength of the pumping radiation, and the resonance frequencies of the nanocavities. In addition the pumping frequency of the dye is selected to be close to the absorption maximum.

Abstract: An LED package and method for LED packaging is disclosed. In one embodiment, an LED package includes a carrier substrate having a predefined surface area, an LED device bonded to the carrier substrate, the LED device having a footprint area of at least fifty percent of the predefined surface area of the carrier substrate, and an encapsulant lens having a top surface inclined inwardly at an angle in the range of about 10° to about 140°. In one embodiment, the top surface of the encapsulant lens layer has a concave cone shape. In one embodiment, a wafer level packaging process includes forming an encapsulant lens layer portion having a top surface inclined inwardly at an angle in the range of about 10° to about 140° on each of a plurality of LED devices bonded to a carrier substrate wafer.

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a first and second fin overlying a substrate, where the first and second fins intersect at a fin intersection. The first fin has a first fin left end. A tunnel dielectric and a floating gate are formed adjacent to the first fin with the tunnel dielectric between the floating gate and the first fin. An interpoly dielectric is formed adjacent to the floating gate, and a control gate is formed adjacent to the interpoly dielectric such that the interpoly dielectric is between the floating gate and the control gate. The control gate, interpoly dielectric, floating gate, and the tunnel dielectric are removed from over the first fin except for at a floating gate position between the first fin left end and the fin intersection.

Abstract: A servo system includes multiple servo channels being driven by a common error signal. Each channel has a controller that receives an error signal and provides a drive signal to a driver. The servo channels are arranged serially, with a drive signal from one controller forming the error signal for a downstream controller. As a result, the downstream controller does not attempt to correct for phase error directly, but instead attempts to keep the upstream driver at or near its operational midpoint. The servo channels can be arranged in order of decreasing controller bandwidth, from fastest to slowest. In contrast with a parallel configuration, in which servo channels all simultaneously receive a common error signal, the serial configuration can allow each controller to use its full bandwidth, can eliminate crosstalk between servo channels, and can prevent saturation of upstream drive signals.

Abstract: A device package method and structure thereof. The method includes steps of: providing a base and a cover, and placing a sensing device on the bottom of cavity base; placing sealant between the cover and edge part of the base, and then covering the cover on the base; irradiating a laser on the edge part for melting the sealant, so as to bond the cover and edge part; and enabling the sealed space formed between the cover and the cavity base to be in vacuum. Therefore, sensing element with high sensitivity can be packaged and manufactured efficiently.

Abstract: Microelectronic packages and methods for fabricating microelectronic packages having texturized solder pads, which can improve solder joint reliability, are provided. In one embodiment, the method includes forming a texturized dielectric region having a texture pattern, such as a hatch pattern, in an under-pad dielectric layer. A texturized solder pad is produced over the texturized dielectric region. The texturized solder pad has a solder contact surface to which the texture pattern is transferred such that the area of the solder contact surface is increased relative to a non-texturized solder pad of equivalent dimensions.