Abstract: A peripheral device is connectable to a computer having one of a first interface and a second interface. The first interface communicates with the peripheral device over a differential data connection having a first data conductor and a second data conductor. The second interface communicates with the peripheral device over a clock conductor and a single ended data connection which includes a data conductor. The peripheral device has first and second communication conductors configured for connection to the first and second data conductors in the differential data connection when the computer includes the first interface and is configured for connection to the first data conductor in the single ended data connection and the clock conductor when the computer is provided with the second interface.

Abstract: An automated method for designing an integrated circuit layout using a computer based upon an electronic circuit description and based upon cells which are selected from a cell library, each of the cells having an associated area, comprising the steps of: (a) placing each of the cells in the integrated circuit layout so that the cells can be coupled together by wires to form a circuit path having an associated predetermined delay constraint wherein the cells are coupled together based upon the electronic circuit description input to the computer; (b) connecting the cells together with the wires to form the circuit path; and (c) adjusting an area of at least one of the cells to satisfy the associated predetermined delay constraint of the circuit path.

Abstract: A method of determining interconnect routes from a plurality of inner leads to lands 32 arranged in a matrix around the inner leads.

Abstract: A method and implementing system is provided in which input signal specifications, element internal delays and output loads, for each element in a circuit design, are utilized in an iterative processing engine to objectively determine and provide a timing rule database for a circuit being designed. A schematic database netlist is run through a test model converter program to provide a test model database at a gate level for the test model design circuit. These data are processed by a designer through a workstation GUI and the result is applied to an I/O design testing function. The results of the I/O design testing function include a listing of patterns of input combinations which are needed to get listed outputs. The GUI prepares a sequence of stimuli to test the circuit with a timing simulator. Based on the output response of the timing simulator, delay relationships under various input and output load conditions are compiled.

Abstract: Automatic routing device which automatically conducts placement and routing of integrated circuits on an integrated circuit chip, including a wire capacitance calculating unit, a degree of wire congestion calculating unit and a routing checking unit for determining whether routing of a desired net is possible or not based on a degree of wire congestion at each global routing cell boundary formed by the division of a logic circuit chip to be processed into global routing cells, and a number of grids calculating units, a grid use rate calculating unit and a grid use rate checking unit for determining whether routing of a desired net is possible or not based on a state of the use of a routing track grid in each global routing cell formed on the logic circuit chip.

Abstract: The present invention resolves the problems of conventional top down hierarchical layout design methods by including the following in a top down hierarchical layout design method using soft block, in addition to determining the arrangement of block pin (called “soft pin”) in soft block, generating second block pin having the same potential as existing block pin; and moving block pin position to position opposite the block pin to be connected. The layout tool program of the present invention is therefore provided the functions of moving and generating soft pin, whereby the top level signal wiring in the region among the blocks is optimized, delay time is minimized, and the use of wasteful wiring channel is avoided for any combination of blocks.

Abstract: A process sort test circuit and methodology for determining performance characteristic of an IC chip. The circuit is located on an IC chip itself and comprises an input for receiving an input signal; a first path from the input to a first output for transmitting the input signal to the first output, the first path sensitive to variations in a manufacturing process for the IC chip; a second path from the input to a second output for transmitting the input signal to the second output, the second path being substantially less sensitive to the variations in the manufacturing process for the IC chip; and, a pulse generator device coupled to the first and second outputs for detecting a difference in arrival times of the input signal at the first and second outputs and for outputting a sort signal if the difference is of a preselected magnitude. The sort signal enables output indication of a performance characteristic of the IC chip.

Abstract: A method and apparatus for the correction of integrated circuit layouts for optical proximity effects which maintains the original true hierarchy of the original layout is provided. Also provided is a method and apparatus for the design rule checking of layouts which have been corrected for optical proximity effects. The OPC correction method comprises providing a hierarchically described integrated circuit layout as a first input, and a particular set of OPC correction criteria as a second input. The integrated circuit layout is then analyzed to identify features of the layout which meet the provided OPC correction criteria. After the areas on the mask which need correction have been identified, optical proximity correction data is generated in response to the particular set of correction criteria. Finally, a first program data is generated which stores the generated optical proximity correction data in a hierarchical structure that corresponds to the hierarchical structure of the integrated circuit layout.

Abstract: A method of designing a cascade decomposed sequential circuit is described in which an input state graph for a sequential circuit is used to generate functions defining transitions between states of the sequential circuit. These functions are used to generate sets of states of the sequential circuit and which contain possible states of the sequential circuit. Levels are then assigned to the generated sets and states are assigned to sequential circuit components in accordance with the assigned levels. These assigned states comprise the current states of the sequential circuit components and using these states and the functions, next states for these sequential circuit components are derived.

Abstract: In accordance with one aspect of the invention, a method is provided for identifying multiple, series-connected pass FETs in an integrated circuit, by evaluating a current node in the netlist to determine whether the current node is a static gate input (or output). If the node is that of a pass gate input (or output), the method then identifies at least one pass FET that is channel-connected to the current node, and determines that an output node (input node) of the at least one pass FET is the same node as the current node. Thereafter, the method reassigns the current node to be an input node (output node) of the at least one pass FET, and repeats the foregoing steps (beginning with identifying at least one pass FET that is channel-connected to the current node). In accordance with another aspect of the present invention, a system is provided for identifying multiple, series-connected pass FETs in an integrated circuit by evaluating a netlist.

Abstract: The routing system implements a global approach (400) that proposes several candidate routes for various nets (402) and analyzes compatibility with respect to other routes and constraints (406), such as electrical or thermal considerations (404).

Abstract: A method, and a system for employing the method, for compacting the amount of memory required to store a two dimensional array of exposure spot shapes in a numerically controlled (NC) electron beam lithography tool. The method includes the steps of: sorting the shapes in a selected line based on the widths and heights of the shapes; identifying and removing from contention a group of shapes in the selected line having common widths and heights; determining a dosage requirement for the shapes in the group; and applying one or more commands based on the group and the determined dosed requirement to enable the NC electron beam lithography tool to draw the two dimensional array of exposure spot shapes.

Abstract: An integrated circuit (IC) module, such as a Single In-Line Memory Module (SIMM), Dual In-Line Memory Module (DIMM), or Multi-Chip Module (MCM), includes a buffering IC that buffers clock and other input signals received by the IC module. As a result of the buffering, the setup and hold times associated with these input signals are improved, thereby improving yields.

Abstract: A design tool to support design of logic circuits is described. The designer develops a syntax statement that comprises encoded information to a defined syntax governing signal naming, logical function, and circuit performance. The encoded syntax statement describes the desired logical function of the logic circuit and the specific configuration of transistors required to build the logic circuit. The syntax statement is provided to a compiler that processes and decodes the syntax statement, and generates from the syntax statement a behavioral model of the logic circuit and a physical circuit description of the logic circuit.

Abstract: A method (and a system for using the method) for placing a semiconductor circuit device between a driver and one or more receivers on the floor space of a chip. The method includes the steps of: determining respective distances between the driver and each of the one or more receivers; determining a shortest of the distances; determining midpoint along the shortest distance; determining whether the midpoint is predesignated to the floor space of one or more blocking semiconductor circuit devices; placing the repeater at the midpoint if the midpoint is not predesignated to the one or more blocking semiconductor circuit devices; and applying a backoff algorithm to incrementally back away from the midpoint to an optimal location, and placing the repeater at the optimal location, if the midpoint is predesignated to the one or more blocking semiconductor circuit devices.

Abstract: A state machine is disclosed that is capable of providing improved performance as realized in a hardware embodiment while providing the flexibility of a software implemented state machine. The state machine is first implemented in software, and then is realized in a hardware embodiment based upon the software implemented state machine. Flexibility is added to the hardware realized state machine by providing registers for the hardware embodiment so that the register corresponds to states of the software implementation. As a result, at least one aspect of the hardware realized state machine may be modified without requiring redesigning the configuration of the hardware embodiment.

Abstract: A process for mapping logic nodes to a plurality of sizes of lookup tables in a programmable gate array. A node and its predecessor nodes are selectively collapsed into a first single node as a function of delay factors associated with the plurality of sizes of lookup tables and a maximum of delay factors associated with the predecessor nodes. If a cut-size associated with the first single node is less than or equal to one of the sizes of lookup tables, the one size is selected to implement the first single node. If a lookup table size was not selected for the first single node, the node and its predecessor nodes are selectively collapsed into a second single node as a function of the delay factors and the maximum delay factor increased by a selected value. If a cut-size associated with the second single nodes is less than or equal to one of the sizes of lookup tables, the one size is selected to implement the second single node.

Abstract: By reusing circuit information designed in the past, the amount of computation for combining circuit information for layout and wirings is significantly reduced. A memory part stores a plurality of pieces of circuit information for forming circuits in programmable logic circuits. Each of pieces of the circuit information has an identifier of its own circuit information, and in the case where part or all of the circuit information is formed with other circuit information, has the identifiers of the other circuit information as reference identifiers, as circuit data thereof. An acquisition part passes specification circuit information from an application program to an editing part, obtains circuit information of a specified circuit, sent from the editing part, and forms the specified circuit in the programmable logic circuits according to the circuit information.

Abstract: A technology mapping method and device for mapping cost functions on directed acyclic graphs, using decoupled matching and covering and circumventing the memory explosion usually caused by this decoupling. Multiple matches are generated at the head of a wavefront process and embedded within the network. Covering is done at the tail of the wavefront to optimize one or more cost functions.

Abstract: An EDA tool is provided with a placement and routing (P&R) module that optimizes placement and routing of an IC design in an interconnect delay driven manner. The P&R module systematically determines if it can improve (i.e. reduce) interconnect delay of the current critical interconnect routing path by determining if it can improve the interconnect delays of its constituting segments, each interconnecting two pins through a component. For each segment, the P&R module determines if the interconnect delay can be achieved by using different interconnect routing path interconnecting the two pins through the component replaced at a different location, and alternatively, through a logically equivalent component disposed at a different location.