Abstract: The method and apparatus for performing design rule checking on Manhattan structures in VLSI circuit layouts. The method and apparatus provides an edge-endpoint-based technique for checking the geometry and spacing of the VLSI circuit layout. The edge-endpoint-based technique uses a scanline algorithm that detects errors between adjacent structures that do not simultaneously intersect the scanline. The method also provides efficient error compilation. The apparatus allows for the design rules to be changed as the VLSI circuit layout evolves. The apparatus can process the VLSI circuit layout with a single processor, and the apparatus provides for multiple processors to process slices of the VLSI circuit layout, thereby enhancing the speed of the design rule checking over traditional software-only techniques.

Abstract: Method and apparatus for managing data on DASD units to improve system performance comprises monitoring portions of data on a plurality of DASD units to determine the times the data is accessed within a given time period, and characterizing accessed data portions of a DASD unit as HOT and COLD data. The DASD units are monitored to determine the number of times each unit is accessed within a time period to develop utilization factors reflective of the number of times the DASD unit is accessed during the time period. HOT and COLD data is moved between DASD units based on the utilization factors of the DASD units.

Abstract: A method is presented that may reduce the number of I/O transactions needed to transfer data between a host device and peripheral device over a parallel port. According to one embodiment, only two I/O transactions are needed to transfer a byte of data as opposed to the eight I/O transactions need in the IEEE 1284-1994 standard. During the two I/O transactions (e.g., transferring data from the host device to the peripheral device), the host device places the data on the data signal lines of the parallel port and toggles a signal on one of the control signal lines. In response, the peripheral device reads the data from the parallel port. Additional bytes can be sent by placing the data onto the port and toggling the signal on the same control signal line. Using this method, a data rate of approximately 4 Mega bits per second may be achieved.

Abstract: Optimal layout of logic elements of semiconductor integrated circuits is achieved in conformity with the intention of the logic designer in a short period of time in an interactive mode. When logic blocks are to be laid out on a display screen, a logic block file consisting at least of logic block names, logic block sizes, and information on connection relationships with other logic blocks is used, and logic blocks essential for the designer's intention are laid out in random positions on a display screen, and then the connection relationships among the logic blocks are displayed according to the logic block file. In this procedure, whether the layout is appropriate or not is made readily recognizable by a table of relationships among the logic blocks.

Abstract: A preamplifier chip for a disk drive is modular in layout. Twelve head cells for the preamplifier chip are not lined along the periphery of the chip, but rather are disposed in an array including four rows of three head cells each. The rows are all directed perpendicular to the side with control connection pads. The preferred embodiment allows for a smaller preamplifier chip through increasing the density of head cells on the chip relative to the periphery of the chip usable for head cell connection. The array spaces write portions of the head cells in four spaced lines, minimizing problems associated with heat build up. Spacing between rows of the array can be determined to take maximum advantage of lead pitch on the flex circuit. Modification of the design to a chip for eight or four channels is possible with minimal changes to the design, and minimal reworking of the common circuitry.

Abstract: The element to be simulated is divided into regions, and each region is further divided into a plurality of quadrature nodes. Pairs are formed for all the quadrature nodes. Green's functions are computed and stored for the pairs. Each of the pairs is allocated to either the far field or the near field for purposes of simulation in accordance with a criterion. A Gaussian quadrature is computed for the pairs allocated to the far field while a high order quadrature is computed for those allocated in the near field. The component simulation is arrived after combining information derived from the Gaussian quadrature and the high order quadrature into a matrix which is then solved to obtain the charge distribution. Summation of the charges thus obtained yields the capacitance of the element. The high order quadrature is computed using a plurality of basis functions. The basis functions, denoted &psgr;ik(r′), are 1,x,y,x2,xy,y2. The basis functions are used to compute a set of weights vjk.

Abstract: A system and method of synthesizing and/or verifying a circuit from a behavioral description of that circuit. A signal ordering of signals in the circuit is defined, wherein defining a signal ordering of signals in the circuit includes specifying a relative ordering of a plurality of events within the circuit. The behavioral description is modified as a function of the signal ordering. The circuit is then synthesized and/or verified as a function of the modified behavioral description.

Abstract: An integrated circuit including a main system processing unit which can be extended using a plurality of programmable logic unit for a plurality of possible functions, and a system for programming same. The integrated circuit also includes a plurality of functional logic blocks, a plurality of input/output (I/O) pads, and programmable logic coupled to each of the plurality of functional logic blocks. The main system processing unit is operable to perform a first function. Each of the plurality of functional logic blocks is operable to perform a respective function. The programmable logic is operable to route data to and from various ones of the plurality of functional logic blocks. The programmable logic is programmable to configure operation of two or more of the plurality of functional logic blocks and is also programmable to create data paths between two or of the plurality of functional logic blocks to configure the integrated circuit for one of the plurality of functions.

Abstract: The object of the procedure according to the present invention is to characterise a voltage or current converter (20) intended to be connected to a capacitive circuit (32) arranged so as to provide a capacitance difference (C1−C2) to the converter. Said converter is arranged so as to be able to receive the capacitance difference provided by the circuit, and to provide an output voltage (Vo) which is a function of the capacitance difference and a bias signal. This procedure is characterised in that it includes a sequence of steps which consist in varying the bias signal, while keeping the capacitance difference constant and measuring in response the output voltage. One advantage of such a procedure lies in the fact that it allows the electric performance of the converter to be determined independently of the error link to the capacitance measuring.

Abstract: A method for verifying all intermediate results of a set of architected registers at the end of an instruction stream, even if the final values do not depend on the values of all intermediate results, using a single MISR (Multiple Input Shift Register) to generate a signature of all updates to multiple architected registers. Single instructions update multiple registers across multiple machine cycles, and an accumulation register allows order independence of partial results. A register update consists of the data to be written, an address identifying which register is to be updated, and controls to identify if this is the last register update that will be done by the current instruction. For each cycle, logic evaluates the update controls to select what will be gated into the accumulation register and also sets MISR control latches to tell how to update the MISR the next cycle. The latched MISR controls select whether the MISR will clear, hold, or evaluate.

Abstract: A methodolgy is described which allows a variety of optical proximity corrections to be added to a mask pattern at low cost and with a view to minimizing the number of electron beam exposures that will be needed later when the reticle is prepared. The basic approach is to add serifs and/or hammerheads to the vertices of the mask pattern on the basis of a small number of simple rule checks. The first check is for the presence of an overlapping pattern at the next level. If this is not detected noting is added at the vertex in question. If some overlap is etected, a predefined search area (at the same mask level) is quickly scanned and, if another stripe is found to be located within a preset distance, serifs are added at the appropriate vertices. If no stripe was found, a second search area, further away, is scanned and if a neighbouring stripe is detected this time, larger serifs are added. If the second search also comes up empty, a hammerhead is added at the appropriate line end.

Abstract: Methods of designing integrated circuit gate arrays include the step of generating a netlist for a gate array integrated circuit having at least first logic and signal resources therein, directly from bitstream data which characterizes a programmable logic device having a first operational functionality and the first logic and signal resources as well. The generating step is also followed by the step of using the netlist to configure the first logic and signal resources within the gate array integrated circuit to provide the first functionality. A preferred integrated circuit design system is also provided and includes a programmable logic device having pre-programmed logic and signal resources therein and a gate array device having base logic and signal resources therein which are equivalent to the unprogrammed logic and signal resources of the programmable logic device.

Abstract: Described is a method of using place-holding cells, or “stopper cells,” to force a place-and-route tool to route a selected signal path through a particular physical location on a semiconductor die. In one method, phantom blocks, created from the design specification, define the area, logic, timing, and the placement of input/output (I/O) ports for a number of custom blocks. These phantom blocks are combined with any standard blocks to create a high-level description of a desired circuit. Then, for each I/O port of the custom blocks, a place-holding cell, or “stopper cell,” is added to the description in the path defined between the I/O port and its source or destination. The stopper cells are then grouped with the associated custom blocks and the resulting collection of stopper cells and blocks are placed and routed. Completed custom blocks can then be substituted for respective phantom blocks after place and route. Stopper cells preserve complex routing during this substitution.

Abstract: A method of making an integrated circuit (IC) includes establishing an initial design for a field-programmable gate array (FPGA) to be included in the IC that includes programmable connections that can be programmed to implement a desired function; establishing an underlying physical template for the IC wherein at least a portion of the template is based on the initial design for the FPGA; selecting a specific configuration of the programmable connections in the FPGA; performing a manufacturing process of the IC using the underlying physical template, and, during the manufacturing process of the IC, bypassing selected on-state transistors in the FPGA used to implement the specific configuration of the programmable connections with metal connections while conserving the underlying physical template. An IC includes a semiconductor substrate and an FPGA fabricated on the semiconductor substrate.

Abstract: The invention provides a floor planning technique by which physical blocks having areas sufficiently matching with actual sub circuits can be produced automatically and also a physical block of a shape other than a rectangle can be produced using a very simple technique.

Abstract: A method of simulating a post-exposure bake (PEB) process for chemically amplified resists having photoacids and protection-sites comprises the following steps. First, the initial PEB parameters are input to represent a temperature-time history of the PEB process. Then, the reaction constants and a diffusion coefficient are input to represent the chemically amplified resists. Wherein the reaction constants are temperature-dependent, and the diffusion coefficient is temperature-dependent and protection-site-dependent in the entire course of the PEB simulation. The protection-site concentration of the chemically amplified resists is computed by using an implicit scheme, and the photoacid concentrations are computed in a space occupied by the chemically amplified resists based on the diffusion coefficient by using an implicit scheme.

Abstract: The present invention is generally directed to a system and method for evaluating a netlist of a schematic to detect the output of a clock driver. In accordance with one embodiment of the invention, a method is provided for determining whether a circuit node is an output node of a clock driver circuit. The method includes the steps of ensuring that the node is a clock node, ensuring that the node is a node within an inverter loop, identifying every FET that is channel connected to the node, and, for every identified FET, ensuring that a signal that drives a gate node of the FET also drives a gate node of a different type FET. With these primary tests satisfied, the method determines the node under consideration to be an output node of a clock driver circuit. In accordance with another aspect of the invention, a method determines whether a circuit node is an output node of a clock driver circuit by ensuring that the node is a node within an inverter loop, and ensuring that a gate node of every FET (i.e.

Abstract: The invention provides a functional module model for realizing optimal pipelining. The functional module model includes division line data representing division lines corresponding to positions where pipeline registers can be inserted and delay/area data representing the trade-off relationship between the delay and the area of each division area partitioned by the division lines. By using this functional module model, a pipeline register insertion position is selected among the division lines represented by the division line data, and the delay and the area of each division area are set on the basis of the trade-off relationship represented by the delay/area data. Thus, a pipelined circuit with a minimized area can be synthesized.

Abstract: A method and apparatus for placement into a programmable gate array of input-output (I/O) design objects having different voltage standards. The programmable gate array has a plurality of sites arranged into banks supporting interfaces with a plurality of different input and output voltage standards. In an example embodiment, I/O design objects are placed into IOBs of the programmable gate array by first performing simulated annealing that considers conflicts between design object voltage standards as placed into the IOBs. Then, a bipartite matching is performed using placement results from simulated annealing. Finally, if the bipartite matching does not produce a feasible placement, standards are assigned to the banks based on the previous placement results, and the bipartite matching process is repeated.

Abstract: A redesigning of dynamic logic circuitry inputs into a process implemented in a computer the dynamic logic circuitry to be redesigned as a set of boolean equations. Along a path through the logic circuitry, the logic circuitry is converted into AND and OR books, or blocks of circuitry. Then various portions of these books are compared to a library of AND/OR and OR/AND books. A list of these possible substitutions from the comparison step is produced. From the list, a selection process selects those substitutions providing a best cost benefit.