Abstract: The present invention is a method of recovering a gate-level netlist from a transistor-level netlist by functionally describing each gate to be recovered using a first transistor model; generating a signature for each gate to be recovered; receiving the transistor-level netlist; selecting a set of connected components from the transistor-level netlist; functionally describing the set of connected components using the first transistor model; generating a signature for the set of connected components; comparing the signature of the set of connected components to the signature of each gate to be recovered; if the signature of the set of connected components matches a signature of a to be recovered then determining if the corresponding functional descriptions match; if a match occurs then functionally describing the set of connected components using a second transistor model; comparing the functional descriptions generated for the set of connected components using the first and second transistor models; identifyi

Abstract: In a method of processing figure arrays in a figure processing apparatus, first and second figure arrays are sequentially inputted. A fractionalizing process is selectively performed to divide each of figure elements of the second figure array into a plurality of types of fractions based on presence/non-presence of an overlapping portion between the first and second figure arrays and an array data of the second figure array. The array data indicates an array pitch in each of horizontal and vertical directions and a number of figures in the direction. A figure array of fractions is produced for each type and the produced figure arrays is registered in chain groups which includes a chain group of the first figure array, such that the registered figure arrays have the same array data. Then, a figure operating process is performed to the chain group.

Abstract: A modular distributed I/O system includes a computer coupled to module banks through a network bus. A module bank includes a communication module, terminal bases, and I/O modules. The adjoined terminal bases form a local bus mastered by the communication module. The I/O modules connect to the local bus through terminal bases. I/O modules are pluriform and programmable. The communication module maintains a memory image of the configuration state of each I/O module resident in the module bank. A memory image persists when an I/O module is removed from its terminal base. The memory image is used to configure a new I/O module which is inserted into the same terminal base. The communication module monitors for communication failure on the network bus, and is configured to capture the state of the module bank and automatically restore this captured state after a power-loss event. The terminal bases realize a local bus which includes a parallel bus, a serial bus, and an address assignment bus.

Abstract: Downstream buffer objects are slaved with the immediate upstream buffer object using a conventional “write remaining” method. The write remaining method can be invoked from each of a plurality of modules having access to the read and write pipes, and operates to slave not the data, but wrappers that point to the data and which therefore represent references to a single copy of the data stored as an upstream data buffer object, so that the actual data need exist in only one place after the write remaining method has been invoked, rather than requiring the data to be sequentially copied from one data buffer to the next. This method further has the benefit of allowing control to be returned to the module during the data transfer function, and of allowing additional data to be written to the outbound pipe.

Abstract: A method and apparatus providing a graphical user interface (GUI) that automatically determines timing groups and path groups for a circuit representation. In a first GUI display level, the GUI displays each path group in the circuit and allows the user to change the timing constraints for each path group. In addition, the GUI indicates whether each timing group is activated by a rising or falling clock signal. In addition, the user can define subpaths of a path group. After timing analysis software has analyzed the circuit, by clicking on a timing group in the first GUI display level, the user can view a second GUI display level, which shows details of the paths in the indicated timing group. By clicking on a path in the second GUI display level, the user can view a third GUI display level, which shows a list of each of the elements in the indicated path.

Abstract: A SCSI system including a SCSI controller, daisy-chained SCSI connectors to which SCSI devices are to be connected, and a SCSI cable interconnecting the SCSI connectors. The SCSI controller includes a circuit for controlling a REQ signal that is allowed to flow through two lines in the SCSI cable, and for controlling an ACK signal that is also allowed to flow through another two lines in the SCSI cable. One of the two lines for conveying the REQ signal alternately connects an unused pin and a REC pin of two successive SCSI connectors, and the other of the two lines alternately connects a REQ pin and an unused pin of the two successive controllers. The two lines for conveying the ACK signal interconnect the SCSI connectors in a similar manner. This enables the load capacitance of the REQ and ACK control signal lines to be reduced, thereby ensuring normal operation of up to seven high speed SCSI devices, that is, the maximum number of devices connectable to the SCSI system.

Abstract: A complete procedure for verifying register-transfer logic against its scheduled behavior in a high-level synthesis environment is provided. A new method that is both complete and practical for verification is provided. Hardware verification is known to be a hard problem and the proposed verification technique leverages off the fact that high-level synthesis--performed manually or by means of high-level synthesis software--proceeds from the algorithmic description of the design to structural RTL through a sequence of very well defined steps, each limited in its scope. Equivalence checking task is partitioned into two simpler subtasks, verifying the validity of register sharing, and verifying correct synthesis of the RYL interconnect and control. While state space traversal is unavoidable for verifying validity of the register sharing, irrelevant portions of the design are automatically abstracted out, significantly simplifying the task that must be performed by a back-end model checker.

Abstract: In a home audio visual network including a plurality of devices coupled via an IEEE 1394 bus, a system for accessing a media drive mechanism of a multi-item-type media player. The multi-item-type media player can play any type of disc media item. A media drive mechanism is included within the mutli-item-type media player and is configured to play or record the media item stored within the multi-item-type media player. A computer system is built-in to the multi-item-type media player. A software based media player model executes on the computer system, and in turn, causes the computer system to implement a method of accessing the media drive mechanism. In so doing, the computer system interfaces with a plurality of devices coupled to the multi-item media player via an IEEE 1394 communications link of an IEEE 1394 based network and provides a standardized command set for the media drive mechanism.

Abstract: A modular distributed I/O system includes a computer coupled to module banks through a network bus. A module bank includes a communication module, terminal bases, and I/O modules. The adjoined terminal bases form a local bus mastered by the communication module. The I/O modules connect to the local bus through terminal bases. I/O modules are pluriform and programmable. The communication module maintains a memory image of the configuration state of each I/O module resident in the module bank. A memory image persists when an I/O module is removed from its terminal base. The memory image is used to configure a new I/O module which is inserted into the same terminal base. The communication module monitors for communication failure on the network bus, and is configured to capture the state of the module bank and automatically restore this captured state after a power-loss event. The terminal bases realize a local bus which includes a parallel bus, a serial bus, and an address assignment bus.

Abstract: A transmitting device and a receiving device are interconnected through two transmission paths, i.e. a data signal line for transmitting serial data, and a delimiting signal line for transmitting a delimiting signal. The delimiting signal causes the receiving device to recognize breaks between bits when the consecutive bits of the transmitted serial data have the same value. The level of the delimiting signal remains unchanged in the event of a change in the logical value of consecutive bits of the transmit data. The level of the delimiting signal is changed when consecutive bits of the transmit data have the same value. The receiving end, receiving the data signal and delimiting signal, reads as digital data the logical value of each bit in the data signal by regarding a point of time of a level change in either one of the data signal and delimiting signal as a break between bits.