Patents Examined by Jing-Yih Shyu
  • Patent number: 10318192
    Abstract: A location of a log file is determined, wherein data corresponding to writes is written sequentially starting from a starting block of the log file. A determination is made in the log file of a range of blocks in which data corresponding to a next write is anticipated to be written. Preprocessing operations are performed corresponding to the range of blocks of the log file in which the data corresponding to the next write is anticipated to be written.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin J. Ash, Lokesh M. Gupta, Matthew J. Kalos
  • Patent number: 10318467
    Abstract: Methods, computing systems and computer program products implement embodiments of the present invention that include configuring distributed storage system resources for a distributed storage system. Examples of the storage system resources include a plurality of network segments, one or more network devices coupled to the network, and multiple nodes coupled to the network, the nodes including both frontend and backend nodes. Upon receiving, by a given frontend node in the distributed storage system, an input/output (I/O) request, one or more of the distributed storage system resources required to process the I/O request are identified, and a respective load that the I/O request will generate on each of the identified distributed storage system resources is calculated. The distributed storage system processes the I/O request upon detecting that the respective loads are less than respective available capacities of the identified distributed storage system resources.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zah Barzik, Lior Chen, Dan Cohen, Osnat Shasha
  • Patent number: 10318312
    Abstract: A network adapter includes one or more network ports, multiple bus interfaces, and a processor. The one or more network ports are configured to communicate with a communication network. The multiple bus interfaces are configured to communicate with multiple respective Central Processing Units (CPUs) that belong to a multi-CPU device. The processor is configured to support an Option-ROM functionality, in which the network adapter holds Option-ROM program instructions that are loadable and executable by the multi-CPU device during a boot process, and, in response to a request from the multi-CPU device to report the support of the Option-ROM functionality, to report the support of the Option-ROM functionality over only a single bus interface, selected from among the multiple bus interfaces connecting the network adapter to the multi-CPU device.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: June 11, 2019
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Yuval Itkin, Liran Liss
  • Patent number: 10311011
    Abstract: A bus node is capable of performing a method, for the assigning of bus node addresses to bus nodes of a serial data bus. The method is performed with the aid of bus shunt resistors in the individual bus nodes in an assignment time period. After assigning bus node addresses to the bus nodes of the serial data bus system in the assignment time period, there follows an operating time period. For this purpose, the bus node comprises such a bus shunt resistor. The bus node is characterized by a bus shunt bypass switch which, prior to assigning a bus node address to the bus node in the assignment time period is opened and which after the assignment of bus node address to the bus node in the assignment time period is closed, and which is closed in the operating time period.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: June 4, 2019
    Assignee: Elmos Semiconductor AG
    Inventors: Christian Schmitz, Bernd Burchard
  • Patent number: 10289600
    Abstract: A method for error detection in transmissions on a multi-wire interface includes providing a plurality of launch clock signals, including launch clock signals having a different phase shifts, determining a type of transition in signaling state that will occur on each wire of the 3-wire interface at a boundary between two consecutively transmitted symbols, and selecting one of the plurality of launch clock signals to initiate the transition of signaling state on each wire of the 3-phase interface. Selecting one of the plurality of launch clock signals may include selecting a first launch clock signal when the transition in signaling state terminates at an undriven state, and selecting a second launch clock signal when the transition in signaling state begins at an undriven state. An edge in the first launch clock signal may occur before a corresponding edge in the second launch clock signal.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: May 14, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Dhaval Sejpal, Shih-Wei Chou, Chulkyu Lee, Ohjoon Kwon, George Alan Wiley
  • Patent number: 10289188
    Abstract: In one embodiment, a processor includes: a plurality of cores, at least some having an advanced programmable interrupt controller (APIC) identifier associated therewith; a plurality of power management agents associated with the plurality of cores; and a power controller to receive an indication of an interrupt and a first APIC identifier and send a wake signal and the first APIC identifier to the plurality of power management agents to determine which of the plurality of cores is associated with the first APIC identifier. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventors: Alexander Gendler, Henrietta Bezbroz
  • Patent number: 10282329
    Abstract: A transmission system includes: a master device; and a plurality of slave devices including a first slave device and a second slave device, each of the plurality of slave devices having its own identifier. The master device includes a processor configured to: transmit a control signal of a clock length that the first slave device does not respond to, to the plurality of slave devices at a first timing; and transmit an identifier that identifies the second slave device to the plurality of slave devices at a second timing after the first timing. The second slave device transmits data to the master device when the second slave device receives the control signal and the identifier that identifies the second slave device.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: May 7, 2019
    Assignee: Fujitsu Client Computing Limited
    Inventor: Shigeo Sakuma
  • Patent number: 10282338
    Abstract: A plurality of processor tiles are provided, each processor tile including a processor core. An interconnection network interconnects the processor cores and enables transfer of data among the processor cores. An extension network connects input/output ports of the interconnection network to input/output ports of one or more peripheral devices, each input/output port of the interconnection network being associated with one of the processor tiles such that each input/output port of the interconnection network sends input data to the corresponding processor tile and receives output data from the corresponding processor tile. The extension network is configurable such that a mapping between input/output ports of the interconnection network and input/output ports of the one or more peripheral devices is configurable.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: May 7, 2019
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Liewei Bao, Ian Rudolf Bratt
  • Patent number: 10277774
    Abstract: An information processing apparatus includes a user interface unit configured to receive a function execution request for processes, the function execution request containing designations of an input function and an output function; a search and linkage unit configured to acquire pieces of specifications information indicating functions of an input device and an output device from the respective devices, and generate, based on the pieces of specifications information, a linkage flow indicating an execution sequence and a combination of an input device and an output device which respectively have an input function and an output function designated in the function execution request, the devices executing the functions, respectively, in linkage with each other; and a flow executing unit configured to send process requests to the input device and the output device designated in the linkage flow, respectively.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: April 30, 2019
    Assignee: Ricoh Company, Ltd.
    Inventors: Kazunori Sugimura, Kiyohiro Hyo
  • Patent number: 10268569
    Abstract: Various embodiments include at least one of systems, methods, and software to receive input configuring tests within a computing environment to expose users to standard application or website experiences or test experiences. In some embodiments, multiple tests may be configured to run orthogonally within user experiences without affecting the results of one another. Some such embodiments preserve the ability to execute certain tests in a non-orthogonal manner while other tests are allowed to execute orthogonally.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: April 23, 2019
    Assignee: eBay Inc.
    Inventors: Jasdeep Singh Sahni, Anil Madan, Deepak Seetharam Nadig, Po Cheung, Bhavesh Mistry, John Bodine, Michael Lo
  • Patent number: 10268606
    Abstract: A data storage device access method, a device and a system. The method includes receiving a mode switch control command by a first bus through a first interface of the control device; switching a second interface of the control device to a predetermined mode based on the received mode switch control command. In cases where the second interface is switched to the first mode in accordance with the mode switch control command, the other device connected to a second bus corresponding to the second interface, accesses the data storage device under the control of the control device via the second interface through the second bus. In cases where the second interface is switched to the second mode in accordance with the mode switch control command, the other device directly accesses the data storage device through the second bus without the control of the control device.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: April 23, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventors: Jianjun Xie, Li-wei Chu, Yuhong Fu, Jian Gao
  • Patent number: 10268483
    Abstract: An apparatus, system, method, and program product for managing peripheral devices using a data protocol is presented. A connection module determines one or more communication bus cables that communicatively couple one or more peripheral devices to an information handling device. A data module reads a data packet associated with a peripheral device over each of the one or more communication bus cables. Each data packet includes an identifier for a location where the peripheral device is installed. A topology module determines a cable connection configuration for the one or more communication bus cables and the one or more peripheral devices based on the installation location identifier received from each of the data packets associated with the one or more peripheral devices.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: April 23, 2019
    Assignee: LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE. LTD
    Inventors: Luke Remis, Mark E. Andresen, Wilson Velez
  • Patent number: 10268847
    Abstract: A data card enclosure method and system comprising data card connectors and host interface connectors on a data card housed in the data card enclosure. The data card enclosure method and system provided for connecting the data card connectors and host interface connectors to external communications ports. One or more of the data card connectors may be repurposed as one or more host interface connections or one or more of the host interface connectors may be repurposed as one or more data card connectors.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: April 23, 2019
    Assignee: LDA TECHNOLOGIES LTD.
    Inventors: Sergey Sardaryan, Mariya Sukiasyan, Vahan Sardaryan
  • Patent number: 10268239
    Abstract: A first electronic device comprises a body, a docking portion that is provided on the body and is detachably coupled to the second electronic device, a terminal that comes into contact according to the coupling of the second electronic device, and a controller that identifies the coupling to the second electronic device, determines the basic performance of the second electronic device, determines the extended performance that can be provided by the first electronic device based on the basic performance of the second electronic device, and controls the second electronic device according to the basic performance of the second electronic device and the extended performance.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: April 23, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Park, Han-Kil Yoon
  • Patent number: 10261558
    Abstract: An example modular computing system may include a host unit. The host unit may include a port that includes a data bus and a power delivery bus. The system may further include a controller to populate a message delivery routing table. The message delivery routing table may include a first address for a first module directly connected to the host unit by the port and a second address for a second module indirectly connected to the host unit by the first module. The controller is to communicate with the second module across the power delivery bus based upon the message delivery routing table.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: April 16, 2019
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Roger D. Benson
  • Patent number: 10261557
    Abstract: A USB power-delivery device includes a clock signal generator which stops generation of a clock signal for a dual-role port (DRP) while the USB power-delivery device operates in a low power mode until an attach event occurs, and starts the generation of the clock signal for the DRP after the attach event occurs.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: April 16, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Je Kook Kim
  • Patent number: 10261936
    Abstract: The present subject disclosure provides a PCIe switch architecture with data and control path systolic array that can be used for real time data analysis or Artificial Intelligence (AI) learning. A systolic array is described which analyzes the TLPs received by an uplink port and processes the TLPs according to pre-programmed rules. Then the TLP is forwarded to a destination port. The reverse operation is described as well.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: April 16, 2019
    Assignee: EXTEN Technologies, Inc.
    Inventors: Harish Kumar Shakamuri, Ashwin Kamath, Michael Enz
  • Patent number: 10255222
    Abstract: Systems and methods for sending files or other data wirelessly from a host digital device to an external digital location by, for example, utilizing the host device's existing media card slot. One embodiment of a system and method is able to connect to a host digital device by using a media card connection cable that may comprise a pseudo media card and a connection cable. The cable is connected to a processing circuit. In an exemplary embodiment, the processing circuit may share the use of at least one media card that may store data from the host device. An exemplary embodiment of the processing circuit may be in electrical communication with at least one wireless source such that the at least one wireless source is adapted to transmit an image or other data to a desired external location or locations.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: April 9, 2019
    Assignee: DOVER ELECTRONICS LLC
    Inventor: Dylan T. Seats
  • Patent number: 10248613
    Abstract: Data bus activation in an electronic device is provided. In one aspect, a host circuit determines a cumulative potential representing a cumulative fractional bus activation vote on a data line(s) in the data bus. The host circuit activates the data bus when the cumulative potential is greater than a configurable bus activation threshold. In another aspect, a device circuit(s) determines a selected signal strength threshold that is less than determined signal strength of an incoming signal. Accordingly, the device circuit(s) asserts a fractional potential corresponding to the selected signal strength threshold on the data line(s) as a fractional bus activation vote in the cumulative fractional bus activation vote. By activating the data bus based on the cumulative fractional bus activation vote, the host circuit can support timely data bus activation while preventing the data bus from being falsely activated, thus improving robustness of data bus activation in the electronic device.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: April 2, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Yuval Corey Hershko, Lior Amarilio, Nir Strauss
  • Patent number: 10249353
    Abstract: In an illustrative embodiment, the memory circuit includes first and second data paths on which data is transferred for read and write memory operations and first and second mixer circuits for adjusting the phase of clock signals applied to their inputs. The mixer circuits are cross-coupled so that the outputs of the first and second mixers are both available to both the first and second data paths. One mixer is used to provide a first phase adjusted clock signal for use by the operating circuit and the other mixer is used to provide a second phase adjusted clock signal for use by a following operation whatever that may be.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: April 2, 2019
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Lei Luo