Abstract: A disk drive comprises non-volatile rotatable media and a controller operatively coupled to the non-volatile rotatable media. The controller is configured to receive a series of host commands to be executed by the controller and generate a command execution sequence comprising the series of host commands. A task manager, integral or coupled to the controller, is configured to receive a plurality of background tasks comprising a least two priority background tasks to be executed by the controller along with execution of the series of host commands, and insert one or more of the at least two priority background tasks into the command execution sequence while maintaining a specified ratio of priority background task execution and host command execution substantially constant. The controller is configured to execute the command execution sequence with the one or more inserted priority background tasks.

Abstract: Discussed herein are devices, systems, and methods for efficient sparse matrix factorization. A method can include writing matrix data representing a sparse matrix to a memory, after writing the matrix data to the memory, write data to a control register of a field programmable gate array (FPGA) indicating the matrix data is available for factorization, and in response to either of (i) reading a status register indicating that the FPGA has factorized the matrix data, or (ii) receiving a software interrupt indicating that the FPGA has factorized the matrix data, determining a solution to a linear system of equations represented by the sparse matrix.

Abstract: System and techniques for enhanced electronic navigation maps for a vehicle are described herein. A descriptor set-up message may be received at a network controller interface (NIC). Here, the descriptor set-up message includes an ethernet frame descriptor. The NIC may then use the ethernet frame descriptor to transmit, across a physical interface of the NIC, multiple ethernet frames, each of which use the same ethernet frame descriptor from the set-up message.

Abstract: A portable computer-peripheral apparatus comprises a Universal Serial Bus (USB) connector. The apparatus is operable to communicate with a computer terminal (e.g. a ‘PC’). Following connection to the PC, the apparatus initialises (i.e. presents or enumerates itself) as a HID keyboard and then sends to the terminal a first predefined sequence of keycodes automatically without manual interaction; the keycodes complying with the human interface device (HID) keyboard standard protocol. Each keycode represents and simulates a keystroke, such as those performed when a user strikes a key on the PC keyboard. The keycode sequence automates the direct access to content, and/or or the initiation of a task or other process.

Abstract: A memory system includes a dynamic random access memory (DRAM) device, a second memory device, and a memory controller circuit. The memory controller circuit is coupled to the DRAM device by a first data channel configured to transfer first data between the memory controller circuit and the DRAM device on behalf of a host, and is also coupled to the DRAM device by a second data channel configured to transfer second data between the memory controller circuit and the DRAM device on behalf of the second memory device while the first data is being transferred across the first data channel.

Abstract: A single-wire bus (SuBUS) apparatus is provided. The SuBUS apparatus includes a master circuit coupled to a slave circuit(s) by a SuBUS. The master circuit can enable or suspend a SuBUS telegram communication over the SuBUS. When the master circuit suspends the SuBUS telegram communication over the SuBUS, the slave circuit(s) may draw a charging current via the SuBUS to perform a defined slave operation. Notably, the master circuit may not have knowledge about exact completion time of the defined slave operation and thus may be unable to resume the SuBUS telegram communication in a timely manner. The slave circuit(s) can be configured to generate a predefined interruption pulse sequence to cause the master circuit to resume the SuBUS telegram communication over the SuBUS. As such, it may be possible for the master circuit to quickly resume the SuBUS telegram communication, thus helping to improve throughput of the SuBUS.

Abstract: A data transfer method includes: instructing a first memory storage device to disable a data encryption function activated by default; and sending a write command to the first memory storage device under a status that the data encryption function of the first memory storage device is disabled. The write command instructs a storing of encryption information of encrypted data to the first memory storage device. The encryption information is not generated by the first memory storage device and is unreadable by a normal read command.

Abstract: A portable memory device includes an interface enabling communications between the portable memory device and an external device; a group of components arranged to provide a certain non-volatile electronic data storage when coupled to the interface. The coupling is performed based on one or more control signals, or on one or more configurations of one or more physical control elements that are transitionable by hand to different configurations, or both. When the group of components and the interface are coupled, the certain non-volatile electronic data storage is provided for use by an external device through the interface; when the group of components and the interface is not coupled or are decoupled, the certain non-volatile electronic data storage is not provided and instead another non-volatile electronic data storage may be provided or none at all. The portable memory device preferably is a flash memory apparatus and may encompass multiple flash-memory drives.

Abstract: A PCIe controller and a loopback path using the PCIe controller. The PCIe controller includes: a transport layer transmission module, a transport layer reception module, a memory access module, and a memory, wherein the transport layer transmission module includes a first loopback control module, the transport layer reception module includes a second loopback control module, and the first loopback control module is coupled to the second loopback control module; the memory access module is coupled to the transport layer transmission module and the transport layer reception module, and the memory access module is also coupled to the memory.

Abstract: Methods and systems for conducting vector send operations are provided. The processor of a sender node receives a request to perform a collective send operation (e.g., MPI_Broadcast) from a user application, requesting a copy of data in one or more send buffers by sent to each of a plurality of destinations in a destination vector. The processor invokes a vector send operation from a software communications library, placing a remote enqueue atomic send command for each destination node of the destination vector in an entry of a transmit data mover (XDM) command queue in a single call. The processor executes all of the commands in the XDM command queue and writes the data in the one or more send buffers into each receive queue of each destination identified in the destination vector.

Abstract: A method for storing data may include receiving user data at a group of storage devices, wherein the storage devices are interconnected, erasure coding the user data into redundancy blocks at the group of storage devices, and storing the redundancy blocks on at least two of the storage devices. The erasure encoding may be distributed among at least two of the storage devices. The redundancy blocks may be arranged in reliability groups. The redundancy blocks may be grouped by the storage devices independently of the partitioning of the user data by the user. The method may further include recovering data based on redundancy blocks. A storage device may include a storage medium, a network interface configured to communicate with one or more other storage devices, and a storage processing unit configured to erasure code user data into redundancy blocks cooperatively with the one or more other storage devices.

Abstract: Launching data stores when new computing infrastructure is deployed is described. A proxy data storage service may be provided that receives instances of an application programming interface (API) call to store data and determines one of a first data store or a second data store to store the data. For instance, in response to receipt of a first instance of the API call, the proxy data storage service may store data in a first data store. However, after a provisioning of the second data store, the proxy data storage service may store data in the second data store in response to receipt of a second instance of the API call. In an instance in which the data stored in the second data store also exists in the first data store, the data is deleted from the first data store until an eventual migration of data is achieved.

Abstract: An interface circuit of a memory device including a plurality of memory dies including a plurality of registers corresponding to the plurality of memory dies, respectively, the plurality of registers each configured to store command information related to a data operation command, a demultiplexer circuit configured to provide input command information to a selected register from among the plurality of registers according to at least one of a first address or a first chip selection signal, the input command information being received from outside the interface circuit, and a multiplexer circuit configured to receive output command information from the selected register from among the plurality of registers and output the output command information according to at least one of a second address or a second chip selection signal may be provided.

Abstract: Embodiments herein provide a Non-Volatile Dual In-Line Memory Module (NVDIMM) device assisted operations management method. The method includes on sending, by the host, a read command to the NVDIMM device receiving, by the host, an URGENT signal upon which it issues a SEND Command and receives a message packet form the NVDIMM device, wherein the message packet comprises information about a time required by the NVDIMM device to read the particular data and an information about operations at the NVDIMM device. Further, the method includes performing, by the host, configuration of the host in a power down mode based on the time required by the NVDIMM device to read the particular data and an information about operations at the NVDIMM device, or performing scheduling operations based on time required by the NVDIMM device to read the particular data and the information about operations at the NVDIMM device.

Abstract: In an example of the described techniques, a wireless communication system includes first memory, second memory, a direct memory access (DMA) controller, an encryption engine in-line between the DMA controller and the second memory, a first microprocessor, and a second microprocessor. The first microprocessor communicates with other systems that generate application data to be wirelessly transmitted. The application data to be wirelessly transmitted is stored in the second memory and programs the DMA controller to transfer packets of the application data to the first memory from the second memory. The encryption engine receives the packets of the application data from the DMA controller, encrypts the packets to generate encrypted application data packets, and outputs the encrypted application data packets for storage to the first memory.

Abstract: A memory system includes: a plurality of nonvolatile memories; a controller connected to the plurality of nonvolatile memories via a plurality of channels that includes a plurality of memory physical layer circuits arranged corresponding to the plurality of channels, respectively, one or more pads for calibration corresponding to the plurality of memory physical layer circuits, and a processor that controls the plurality of memory physical layer circuits. A single reference resistor is connected to the plurality of memory physical layer circuits via the pad. An output based on a ZQ calibration of the plurality of memory physical layer circuits is wired-OR connected to the single reference resistor via the one or more pads. The processor performs a calibration for each of the plurality of memory physical layer circuits in a time division manner using the single reference resistor.

Abstract: Described is a method and apparatus for application migration between a dockable device and a docking station in a seamless manner. The dockable device includes a processor and the docking station includes a high-performance processor. The method includes determining a docking state of a dockable device while at least an application is running. Application migration from the dockable device to a docking station is initiated when the dockable device is moving to a docked state. Application migration from the docking station to the dockable device is initiated when the dockable device is moving to an undocked state. The application continues to run during the application migration from the dockable device to the docking station or during the application migration from the docking station to the dockable device.

Abstract: A memory device stores data for a host. In one approach, a trim operation is initiated for the memory device (e.g., based on a context that is determined for the memory device). During the trim operation, read and/or write tests are performed on one or more portions of a non-volatile storage media of the memory device. One or more characteristics associated with the memory device are observed during the test. Based on these observed characteristics, one or more trim settings are determined. Then, the memory device is updated to store the determined trim settings to configure subsequent read or write access to the non-volatile storage media (e.g., access performed in response to commands from a host).

Abstract: Systems and methods are provided for addressing die are inefficiencies associated with the use of redundant ternary content-addressable memory (TCAM) for facilitating error detection and correction. Only a portion of redundant TCAMs (or portions of the same TCAM) are reserved for modified coherency directory cache entries, while remaining portions are available for unmodified coherency directory cache entries. The amount of space reserved for redundant, modified coherency directory cache entries can be programmable and adaptable.

Abstract: Provided herein may be a priority determination circuit and a method of operating the priority determination circuit. The priority determination circuit may receive request signals from a plurality of microcontrollers respectively corresponding to the plurality of planes, and output response signals corresponding to the request signals depending on a determined priority.