Abstract: Techniques for loading data, comprising receiving a memory management command to perform a memory management operation to load data into the cache memory before execution of an instruction that requests the data, formatting the memory management command into one or more instruction for a cache controller associated with the cache memory, and outputting an instruction to the cache controller to load the data into the cache memory based on the memory management command.

Abstract: A memory card includes a first surface, a second surface, and 1st to Nth terminal groups. The first surface includes first to Nth rows, wherein N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1st to Nth terminal groups are placed in the first to Nth rows. The 1st terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. Kth terminal group, wherein K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.

Abstract: A device may include a connector to connect the device to a chassis. The device may include chassis type circuitry to determine a type of the chassis. The device may further include mode configuration circuitry to configure the device to use a particular mode appropriate for the type of the chassis.

Abstract: A host device discovers one or more first protocol endpoints presented by a storage system for a first logical storage device utilizing a first access protocol, and discovers one or more second protocol endpoints presented by the storage system for a second logical storage device utilizing a second access protocol. Responsive to determining that the first and second logical storage devices have a same device identity, the host device temporarily masks the one or more second protocol endpoints in a multi-path layer of the host device from one or more applications executing on the host device. In conjunction with a switchover from the first logical storage device to the second logical storage device, the host device ends the temporary masking in the multi-path layer and enables access of the one or more applications to the second logical storage device via the one or more second protocol endpoints.

Abstract: The subject technology receives code corresponding to a neural network (NN) model, the code including particular operations that are performed by the NN model. The subject technology determines, among the particular operations, a set of operations that are to be allocated to a cache of the electronic device that is to execute the NN model. The subject technology generates a set of cache indicators corresponding to the determined set of operations. The subject technology compiles the code and the generated set of cache indicators to provide a compiled binary for the NN model to execute on a target device.

Abstract: A method for adaptively identifying flash memory type includes driving a flash memory interface according to a predetermined configuration and a predetermined protocol of the flash memory interface to send a reading command to a flash memory module to obtain a flash memory identity by successfully reading the flash memory module; changing at least one of the configuration and the interface protocol of the flash memory interface then performing the obtaining the flash memory identity again until all preset adjustments have been tried; and storing the obtained flash memory identity and a firmware corresponding to the obtained flash memory identity to a designated address of a non-volatile memory when the flash memory module is successful read. The above automated method can solve the disadvantages of high cost and low manufacturing flexibility caused by conventional manual identification and re-burning of eFuses.

Abstract: A device may include a connector to connect the device to a chassis. The device may include chassis type circuitry to determine a type of the chassis. The device may further include mode configuration circuitry to configure the device to use a particular mode appropriate for the type of the chassis.

Abstract: Techniques are provided for overlapping write handling. Overlapping write managers are used to maintain the order that write operations are executed at a first computing environment and replicated to a second computing environment. Overlapping write managers are pre-allocated as available for managing overlapping write operations. A mapping is used to track what overlapping write managers are currently allocated for particular file handles of files. Thus, if an incoming write operation targets a file handle of an already allocated overlapping write manager, then that overlapping write manager is used to execute and replicate the incoming write operation so that the order of execution of overlapping writes by the second computing environment is the same as at the first computing environment. If there is no allocated overlapping write manager for the file handle, then a new overlapping write manager is allocated and utilized.

Abstract: A initialization code/data memory mapping system includes a processing system, memory device(s) storing initialization code and initialization data, and a main memory system. The processing system performs first MMIO read operations to access the initialization code stored in the memory device(s) that is mapped to an initialization memory space in order to provide an initialization engine, and uses it to copy the initialization code from the memory device(s) to the main memory system. The processing system then accesses the initialization code stored in the main memory system in order to provide the initialization engine, and uses it to map the initialization data stored in the memory device(s) to the initialization memory space. The processing system then performs second MMIO read operations to access the initialization data stored in the memory device(s) that is mapped to the initialization memory space for use by the initialization engine.

Abstract: The present technology includes a controller including an allocation manager configured to determine whether a host identification (ID) output from a host is an allocable ID, an address manager configured to perform an allocation operation using the host ID to select logical blocks corresponding to the host ID when the host ID is received from the allocation manager, and output an address of the logical blocks as an allocation address, and a map table component configured to store a map table in which logical block addresses and physical block addresses are respectively mapped, select a logical block address corresponding to the allocation address, and output the physical block address mapped to the selected logical block address, a memory system including the controller, and a method of operating the memory system.

Abstract: Systems and methods for managing transfer of NVMeoF commands/responses between a host and a target are described. The systems and methods may initiate and convert at least one Input/Output request into at least one Non-Volatile Memory Express over Fabric (NVMeoF) command to access a storage device attached with the target device. A host may transmit the at least one NVMeoF command in a burst mode using a Remote Direct Memory Access (RDMA) Write packet to a pre-registered memory region of the target device. In response to reception of the at least one NVMeoF command, the target device may post at least one NVMeoF completion response corresponding to the at least one NVMeoF command using the RDMA Write packet to a pre-registered memory region of the host.

Abstract: Selective honoring of speculative memory-prefetch requests based on bandwidth constraint of a memory access path component(s) in a processor-based system. To reduce memory access latency, a CPU includes a request size in a memory read request of requested data to be read from memory and a request mode of the requested data as required or preferred. A memory access path component includes a memory read honor circuit configured to receive the memory read request and consult the request size and request mode of requested data in the memory read request. If the selective prefetch data honor circuit determines that bandwidth of the memory system is less than a defined bandwidth constraint threshold, then the memory read request is forwarded to be fulfilled, otherwise, the memory read request is downgraded to only include any requested required data.

Abstract: A control device according to the present invention includes: a memory; and processing circuitry coupled to the memory and configured to: detect a state of access to table data stored in a first logical disk of a physical disk and to which first data is written and a state of access to a write ahead log (WAL) stored in a second logical disk of the physical disk and to which second data is written or to a WAL stored in a second storage medium different from the physical disk and to which the second data is written, and acquire an I/O use ratio of the WAL and an I/O use ratio of the table data, and set a writing destination of the second data to one of the WAL stored in the second logical disk and the WAL stored in the second storage medium.

Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.

Abstract: Method and apparatus for managing data in a storage device, such as a solid-state drive (SSD). In some embodiments, write and read commands from a client device are placed into a command queue pending servicing to transfer data between the client device and a non-volatile memory (NVM). A write cache temporarily stores sets of writeback data pending transfer. A cache manager detects an overlap condition in which a subsequently received command at least partially overlaps a pending write command. In response, the cache manager enacts a change in caching policy that includes retention of the cached writeback data to aid in the servicing of the subsequently received command. The changes in caching policy can include an increase in the size of the write cache, delays in the writing of hot writeback data sets, the coalescing of different writeback data sets, cache hits using the cached writeback data, etc.

Abstract: A communications interface for interfacing between a host system and a state machine includes an event slot, the event slot comprising a plurality of registers including: a write register for writing by the host system, and a read register for reading by the host system, wherein the event slot is addressed from the host system by a single address location permitting the host system to write data to the write register and/or read data from the read register; and wherein the write register and the read register are individually addressable by the state machine.

Abstract: Methods, systems, and devices manipulate operation of at least one electronic control unit (ECU) connected to a controller area network (CAN) bus. The at least one ECU includes at least one error counter, by counting errors associated with at least one ECU. The manipulating is based on generating and broadcasting via the CAN at least one bit stream destined to at least one ECU, thereby manipulating at least one ECU status, determined by the ECU error counter and querying for its status state.

Abstract: A control device of the invention for a semiconductor memory device comprising an interface conforming to JEDEC standard of DDRx-SDRAM or LPDDRx-SDRAM, comprises banks, a read/write control circuit, and a transfer control circuit. Each bank comprises subarrays. Each subarray comprises memory cells arranged along bit lines and word lines. The read/write control circuit controls reading of data from and writing of data to the semiconductor memory device. The transfer control circuit controls data transfer inside the semiconductor memory device and sets to enable an additional transfer command not specified in the JEDEC standard and a transfer command for writing data, read from a transfer source memory cell, to a transfer destination memory cell without passing outside the semiconductor memory device by transmitting a first signal value not used in the JEDEC standard to the semiconductor memory device via at least one signal line of the interface.

Abstract: A system includes a NVM memory, and a volatile memory to store: a zone map data structure (ZMDS) that maps a zone of a logical block address (LBA) space to a zone state and to a zone index; a journal data structure (JDS); and a high frequency update table (HFUT). A processing device is to: write, within an entry of the HFUT, a value of a zone write pointer corresponding to the zone index, wherein the zone write pointer includes a location in the LBA space; write, within an entry of the ZMDS, a table index value that points to the entry of the HFUT; update, within the JDS, metadata of the entry of one the ZMDS or the JDS affected by a flush transition between the ZMDS and the HFUT; and in response to an asynchronous power loss event, flush the JDS and the HFUT to a NVM device.

Abstract: Communication fabric-coupled computing architectures, platforms, and systems are provided herein. In one example, an apparatus includes a management entity configured to establish compute units each comprising components selected among a plurality of physical computing components. The apparatus includes a fabric interface configured to instruct a communication fabric communicatively coupling the plurality of physical computing components to establish logical isolation within the communication fabric to form the compute units.