Abstract: In a deep neural network (DNN), weights are defined that represent a strength of connections between different neurons of the DNN and activations are defined that represent an output produced by a neuron after passing through an activation function of receiving an input and producing an output based on some threshold value. The weight traffic associated with a hybrid memory therefore is distinguished from the activation traffic to the hybrid memory, and one or more data structures may be dynamically allocated in the hybrid memory according to the weights and activations of the one or more data structures in the DNN. The hybrid memory includes at least a first memory and a second memory that differ according to write endurance attributes.

Abstract: An apparatus comprises a host device configured to communicate over a network with source and target storage systems. The host device, in conjunction with migration of a logical storage device from the source storage system to the target storage system, is further configured to obtain from the target storage system watermark information characterizing progress of the migration of the logical storage device from the source storage system to the target storage system, and to determine whether a given input-output operation is to be sent to the source storage system or the target storage system based at least in part on the watermark information obtained from the target storage system. The watermark information illustratively identifies a particular logical address in the logical storage device, up to and including for which corresponding data has already been copied from the source storage system to the target storage system in conjunction with the migration.

Abstract: Correlating storage system event alerts by receiving notice of an event, determining a first storage network system (SNS) resource related to the event, determining instantiated dependencies between the first SNS resource and a second SNS resource, correlating the event with a second event according to the instantiated dependencies, and providing notice of the correlated events.

Abstract: In some examples, during execution of an application as an application asset is called, an asset map that is stored in a persistent memory device is searched for an asset identifier associated with the application asset. Using this asset identifier, an application asset stored in the persistent memory device is located. The persistent memory device is directly accessed by a processor executing the application. The processor processes the application asset from its location in the persistent memory device.

Abstract: A method for creating a virtual intermediary filesystem on the fly and in real-time on a compute node cluster having a plurality of compute nodes that are running or scheduled to run an application job is provided The method includes initializing a data structure, allocating a plurality of compute nodes, reserving the compute node cluster, distributing the application job, determining memory utilization, determining potential free memory space, marking the potential free memory space, and mapping the marked potential free memory space to create the virtual intermediary filesystem on-demand and in real-time, wherein the virtual intermediary filesystem is arranged to store data in parallel and concurrently from a plurality of computing devices on the compute node cluster and output the stored data to a storage system, wherein the computing devices output the data at a rate that is greater than a maximum write or read data rate of the storage system.

Abstract: An example apparatus includes a memory, a data writer to write received first data into the memory in a first order, and a data reader to read the first data from the memory in a second order, wherein the data writer is to write second data into the memory in the second order.

Abstract: There is a method and a corresponding system for performing partial write operations to memory. This method and corresponding system utilizes an XOR operation to generate error checking bits. Once the error checking bits are generated, they are then used for error checking a set of data bits so that these data bits can be written to memory.

Abstract: Techniques for optimizing write IO bandwidth and latency in an active-active clustered system using storage object affinity to a single node. The active-active clustered system can include at least a primary storage node and a secondary storage node that maintain their own journals. The respective journals are directly accessible to both storage nodes. The journals are synchronized for each page or entity of a storage object when a storage IO request is issued to a storage node to which the storage object does not have affinity. Such synchronization is performed in the framework of acquiring a lock on the entity of the storage object during internode communications. To facilitate recovery from a disaster, data loss, and/or data corruption, transaction IDs associated with storage IO operations are employed to facilitate identification of the most up-to-date reference or description information for a given data or metadata page of a storage object.

Abstract: A memory block type processing method includes: a state of each memory block in the electronic device is monitored; when it is monitored that a memory block is released, a type of the released memory block is detected; responsive to that it is detected that an original type of the released memory block is inconsistent with a present type of the released memory block, a released memory capacity of the released memory block is detected; and the present type of the released memory block is adjusted according to the detected released memory capacity. Therefore, sufficient regional ranges of memory partitions of the reclaimable and/or movable types can be ensured, and during memory compaction, a continuous memory that is sufficient for a user to use can be effectively provided by compaction to alleviate the memory fragmentation problem.

Abstract: A system includes a memory buffer, a first data processor, a second data processor, and a controller. The first data processor performs a write operation to write data into the memory buffer and provides a first reference indicating a status or progress of the write operation. The controller provides a second reference indicating a buffer block in the memory buffer. The second data processor receives the first reference and the second reference, uses a threshold and the first reference to determine whether the buffer block contains enough data to be processed by the second data processor, obtains data to be processed from the buffer block using the second reference if the buffer block contains enough data to be processed, and processes the data obtained from the buffer block.

Abstract: A memory controller controlling a memory device including a plurality of memory cells includes a read operation controller performing a soft read operation on the plurality of memory cells by using a plurality of soft read voltages determined based on a default read voltage when a read operation for reading the plurality of memory cells by the default read voltage fails, and reading the plurality of memory cells by using an optimal read voltage determined according to a result of performing the soft read operation, and a read voltage setting circuit determining the optimal read voltage using voltage candidates being soft read voltages corresponding to at least two voltage intervals, among a plurality of voltage intervals determined according to the plurality of soft read voltages, the voltage candidates selected in ascending order of a number of memory cells having threshold voltages belonging to each of the plurality of voltage intervals.

Abstract: In a cloud computing environment, a storage space management system provides for uniform collection of usage statistics for storage disks and storage consumers, including usage statistics for a consumers' storage buckets, where a storage bucket represents a logical container of files, objects or other types of stored data for a given consumer. The system enables automated evaluation of space usage policy against the collected statistics. The system enforces the evaluated policy determinations, including queueing jobs that manage storage disk eligibility for storing data and jobs that direct traffic from storage consumers to storage disks that have sufficient storage available.

Abstract: A system-on-chip module for avoiding redundant memory access is provided, comprising at least one microprocessor, a DRAM and a DRAM controller. The DRAM and the microprocessor are integrated and formed in the system-on-chip module commonly. The DRAM controller is electrically connected between the DRAM and the microprocessor, and includes at least one column cache unit such that each microprocessor is able to perform read or write command to the DRAM through its corresponding column cache unit. Compared with the prior arts, the present invention is beneficial to provide better data access quality, efficiency and lower cost and complexity of the system architecture. Thus, the present invention is believed to be applied widely and having greater industrial applicability.

Abstract: A device may include a connector to connect the device to a chassis. The device may include chassis type circuitry to determine a type of the chassis. The device may further include mode configuration circuitry to configure the device to use a particular mode appropriate for the type of the chassis.

Abstract: A data access method. The method is applied to a first controller, and the method includes: receiving a destination address sent by each shared cache apparatus, where the destination address is used to indicate an address at which data is to be written into the shared cache apparatus; receiving information carrying the data; and sending the destination address and the data to the shared cache apparatus that sends the destination address, so that each shared cache apparatus stores the data in storage space to which the destination address points.

Abstract: An apparatus includes: a semiconductor die including a first I/O (input/output) pad, a second I/O pad, a switch, and an internal processor, wherein the switch is configured to short the first I/O pad to the second I/O pad when a control signal is asserted; and a semiconductor package including a first bond pad configured to electrically connect to the first I/O pad, a second bond pad configured to electrically connect to the second I/O pad, a first port configured to electrically connect to a high-speed pin of a multi-mode connector, a second port configured to electrically connect to an external processor, a first routing path configured to electrically connect the first port to the first bond pad, and a second routing path configured to electrically connect the second port to the second bond pad.

Abstract: An apparatus comprises at least one processing device comprising a processor coupled to a memory. The at least one processing device is configured to receive, via a multi-path layer of at least one host device, at least one indication of a predicted distribution of input-output operations directed from the at least one host device to a storage system for a given time interval. The at least one processing device is also configured to determine a cache memory configuration for a cache memory associated with the storage system based at least in part on the at least one indication of the predicted distribution of input-output operations for the given time interval. The at least one processing device is further configured to provision the cache memory with the determined cache memory configuration for the given time interval.

Abstract: A technique provides transitioning from an original device to a new device within a data storage array. The technique involves initiating a copying activity within the data storage array, the copying activity copying data from the original device to the new device. The technique further involves, while the data is being copied from the original device to the new device, routing write requests that target logical storage which is currently supported by the original device to both the original device and the new device. The technique further involves, after the data has been copied from the original device to the new device, performing a configuration change which routes I/O requests that target the logical storage to the new device rather than the original device.

Abstract: A system includes a fabric switch including a motherboard, a baseboard management controller (BMC), a network switch configured to transport network signals, and a PCIe switch configured to transport PCIe signals; a midplane; and a plurality of device ports. Each of the plurality of device ports is configured to connect a storage device to the motherboard of the fabric switch over the midplane and carry the network signals and the PCIe signals over the midplane. The storage device is configurable in multiple modes based a protocol established over a fabric connection between the system and the storage device.

Abstract: An apparatus comprises a host device comprising at least one processor coupled to memory. The host device is configured to communicate over a network with a storage system comprising a plurality of storage devices. The host device is further configured to identify a logical volume identifier corresponding to a given logical volume of the storage system and to submit a message comprising an indication of the logical volume identifier to a messaging system. The host device is further configured to obtain, from the messaging system, an indication of a pseudo name corresponding to the logical volume identifier and to assign the obtained pseudo name to a multipath device corresponding to the given logical volume, the multipath device comprising a plurality of paths between the host device and the given logical volume.