Abstract: A method performed by a memory chip is described. The method includes receiving an activated chip select signal. The method also includes receiving, with the chip select signal being activated, a command code on a command/address (CA) bus that identifies a next portion of an identifier for the memory chip. The method also includes receiving the next portion of the identifier on a portion of the memory chip's data inputs. The method also includes repeating the receiving of the activated chip select signal, the command code and the next portion until the entire identifier has been received and storing the entire identifier in a register.

Abstract: A method for performing adaptive locking range management, an associated data storage device and a controller thereof are provided. The method may include: receiving a security command from outside of the data storage device, wherein the security command is related to changing an old locking range into a new locking range; obtaining a start Logical Block Address (LBA) and a length value of the new locking range according to the security command; determining whether the start LBA of the new locking range is less than an end LBA of the old locking range, and determining whether an end LBA of the new locking range is greater than a start LBA of the old locking range; and in response to both determination results being true, performing data trimming on any respective non-overlapped portions of the new locking range and the old locking range.

Abstract: The present invention provides a microcontroller, wherein the microcontroller includes a processor, a first memory and a cache controller. The first memory includes at least a working space. The cache controller is coupled to the first memory, and is arranged for managing the working space of the first memory, and dynamically loading at least one object from a second memory to the working space of the first memory in an object-oriented manner.

Abstract: Modifications to be made to a page of non-volatile data storage and a current transaction sequence number are store into a protected memory. The current transaction sequence number is added to a previous version of the page and the modifications are applied to the previous version of the page to create a new version of the page that is written to the non-volatile data storage. A failure of the write may cause the stored modifications to be re-applied to the page in response to a transaction sequence number in a retrieved version of the page not matching the saved current transaction sequence number. A write completion status stored in a protected memory may indicate which ones of multiple copies of the page have been overwritten with the new version. Alternatively, an error-detecting code may be generated and written to non-volatile data storage with the new version to the multiple copies.

Abstract: A method and system for proactive data migration across tiered storage that uses machine learning is shown. The method includes receiving first input-output (IO) event metadata describing a first IO event, and analyzing the first IO event metadata using an optimized learning model (OLM), to obtain a first learning model output. The first learning model output is interpreted to generate a first data migration request, and the first data is proactively migrated from a first storage tier to a second storage tier based on the first data migration request.

Abstract: Memory address translation apparatus comprises page table access circuitry to access a page table to retrieve translation data; a translation data buffer to store one or more instances of the translation data, comprising: an array of storage locations arranged in rows and columns; a row buffer comprising a plurality of entries and comparison circuitry responsive to a key value dependent upon at least the initial memory address, to compare the key value with information stored in each of at least one key entry and an associated value entry for storing at least a representation of a corresponding output memory address, and to identify which of the at least one key entry, if any, is a matching key entry storing information matching the key value; and output circuitry to output, when there is a matching key entry, at least the representation of the output memory address.

Abstract: A switch-based inter-device notational data movement system includes a switch device that is coupled to a first processing system included in a first chassis and configured to provide a first thread, a second processing system included in a second chassis and configured to provide a second thread, and a memory system. The switch device identifies, in a communication transmitted by the first thread, a request to transfer data, which is stored in a first portion of the memory system that is associated with the first thread in a memory fabric management database, to the second thread. The switch device then modifies notational reference information in the memory fabric management database to disassociate the first portion of the memory system and the first thread and associate the first portion of the memory system with the second thread, which allows the second thread to reference the data using request/respond operation.

Abstract: A device management server computer (“server”) is programmed to manage a plurality of input devices and output devices in a physical room. The server is programmed to analyze media data capturing actions performed by a user in real time as a participant in the physical room, determine how the user would like to connect at least one of the input devices and one of the output devices from the analysis, and enable the connection. The sever is programmed to interpret the actions and derive commands for connecting two or more devices based on predetermined data regarding the input devices and output devices and rules for referring to and connecting these devices.

Abstract: A method, system, and computer program product are described for a machine selecting a selected adapter among two or more adapters that perform a same function. The method includes generating a request, at the machine, for the function, and calculating a time indicator associated with each of the two or more adapters based on a respective adapter queue time factor (QTF) associated with each of the two or more adapters, the adapter QTF associated with each of the two or more adapters being a computed value. The method also includes selecting the selected adapter and submitting one or more requests to the selected adapter of the two or more adapters to perform the function based on a comparison of the time indicator associated with each of the two or more adapters.

Abstract: A transceiver configured to send and receive data over a data bus is disclosed. The transceiver includes a communication port to connect to the data bus, a bus idle detector configured to detect when the data bus is idle, a TXDC interface configured to selectively receive and send data and an RXDC interface configured to send data. The transceiver also includes a switch controlled by an output of the bus idle detector. The switch is configured to cause the TXDC interface to be used for sending data out when the bus idle detector detects that the data bus is idle.

Abstract: A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.

Abstract: In a memory controller, a prefetch indication can be sent to memory to prepare the memory for a potential future read or write. Statistics can be used to select when such a prefetch should occur. The prefetch can occur without any read or write command being commenced. As a result, the memory controller predicts when to perform the prefetch. Some examples of when a prefetch can be sent include when there are other requests for the same memory page, or how often the page is requested. The page can remain open to prevent it from closing until the relevant read or write arrives. In the case that a read or write does not occur after a predetermined period of time, then a precharge can be performed to release the memory page.

Abstract: A system includes a device that includes one or more pattern-recognition processors in a pattern-recognition cluster. One of the one or more pattern-recognition processors may be initialized to perform as a direct memory access master device able to control the remaining pattern-recognition processors for synchronized processing of a data stream.

Abstract: Systems, apparatuses, and methods related to bit string conversion are described. A memory resource and/or logic circuitry may be used in performance of bit string conversion operations. The logic circuitry can perform operations on bit strings, such as universal number and/or posit bit strings, to alter a level of precision (e.g., a dynamic range, resolution, etc.) of the bit strings. For instance, the memory resource can receive data comprising a bit string having a first quantity of bits that correspond to a first level of precision. The logic circuitry can determine that the bit string having the first quantity of bits has a particular data pattern and alter the first quantity of bits to a second quantity of bits that correspond to a second level of precision based, at least in part, on the determination that the bit string has the particular data pattern.

Abstract: A storage device includes a reconfigurable logic circuit, a control logic circuit, and non-volatile memory. The reconfigurable logic circuit is changeable from a first accelerator to a second accelerator during an operation of the storage device. The control logic circuit is configured to receive, from the host, a host command including information about a function required by the host and dynamically reconfigure the reconfigurable logic circuit such that the reconfigurable logic circuit performs the function according to the received host command. The non-volatile memory is connected to the control logic circuit.

Abstract: Techniques are provided for providing a type-based message bus with message type hierarchies for non-object oriented languages. In an example, a type-aware message bus receives a subscription message from a subscriber that identifies an object-oriented class. The message bus determines an event channel that corresponds to the class, and subscribes the subscriber to the event channel. The message bus also determines any event channels that correspond to a subclass of the class, and subscribes the subscriber to those event channels. When a publisher publishes a message to an event channel, the message bus publishes the message to each subscriber of the event channel, which can have the effect of publishing the message to subscribers that originally subscribed to superclass event channels of the event channel.

Abstract: A Universal Flash Storage (UFS) memory module including an input/output interface, a flash memory and a controller, and a method for operating a UFS memory module are disclosed. The flash memory includes: a write buffer portion; and a normal storage portion having a plurality of logic units. The controller includes: a processor; a first register indicating a maximum size of the write buffer portion; a second register indicating an available size of the write buffer portion; and a third. If the third register indicates the UFS memory module is in a shared buffer mode, the write buffer portion only includes a first shared buffer area. If the third register indicates the UFS memory module is in an advanced mode, the write buffer portion includes at least one dedicated buffer area, each corresponding to one of the plurality of logic units.

Abstract: The hard disk management system includes at least one object server and a managing server. The object server is configured for sending a first request to a managing server to obtain object hard disk information. The managing server is configured for obtaining object hard disk information corresponding to the object server after receiving the first request, and sending the object hard disk information to the object server. The object server is further configured for monitoring and managing a group of object hard disks indicated by the object hard disk information.

Abstract: A semiconductor data storage memory can be arranged with an accumulated list in a memory of background operations to be carried out upon a semiconductor memory formed of one or more non-volatile memory dies. When a deterministic window interval is entered responsive to a request from a host during which data transfers between the host and the semiconductor memory meet a minimum predetermined data transfer rate, the accumulated list is sorted into a first set of the background operations that can be performed during the deterministic window interval while maintaining the minimum predetermined data transfer rate and a remaining second set of the background operations. The first set of the background operations is performed during the deterministic window interval prior to the second set of background operations being performed after a conclusion of the deterministic window interval.

Abstract: A batch automatic test method and a batch automatic test device for solid state disks are provided. The batch automatic test method is used for testing a plurality of solid state disks by a batch automatic test device. The solid state disks are coupled to the batch automatic test device. The batch automatic test method includes the following steps. A plurality of buses of the batch automatic test device are scanned to mark the solid state disks and a system disk. A piece of disk information of each of the solid state disks is shown. Each of the pieces of the disk information includes a disk location of each of the solid state disks. A formatting procedure is synchronously performed on the solid state disks according to the disk locations. After performing the formatting procedure, a burn-in test procedure is automatically and synchronously performed on the solid state disks.