Abstract: A demodulating circuit includes a differentiating circuit that outputs a differentiated signal indicating voltage changes at rising and falling edges of a received pulse signal, and a hysteresis comparator that compares the differentiated signal with upper and lower threshold voltages, thereby generating a demodulated logic-level signal. The differentiating circuit can rapidly track variations in the direct-current offset of the received pulse signal. Positive feedback can enable the hysteresis comparator to maintain the correct output logic level during runs of 0's or 1's of arbitrary length in the received pulse signal. The demodulating circuit consumes comparatively little power, and is particularly useful for receiving signals transmitted in bursts.

Abstract: A method for correcting A/D converted output data which corrects digital data obtained by A/D conversion of an analog signal, comprising forming an at least first order polynomial curve approximating an input/output characteristic curve of A/D conversion in a range of input of the analog signal, setting an ideal input/output characteristic line of A/D conversion, deriving a conversion equation for converting coordinates of a point on the approximation polynomial curve to a point of the ideal input/output characteristic line for the same analog signal value, and using this conversion equation to convert A/D converted digital data so as to correct non-linearity of the output data.

Abstract: In a resonator having a dielectric member and an electrode formed on the dielectric member, a displacement area (D area) having a high vertical electric field component, and a short or steady area (S area) having a vertical electric field component of zero or close to zero are provided in an interface between the dielectric member and the electrode. A single-layer conductive film divided into portions is formed in the D area or on the side surfaces of the dielectric member, and a multilayer thin-film electrode is formed in the S area or on the end faces of the dielectric member. Conductive thin films of the multilayer thin-film electrode are alternately connected to the single-layer conductive film portions. In-phase currents having the same amplitude flow to the conductive thin films of the multilayer thin-film electrode in the S area in radial direction with respect to the axis of symmetry, thus achieving low-loss operation of the multilayer thin-film electrode in the S area.

Abstract: Skew-tolerant Gray codes have the property that consecutive code words differ in only one co-ordinate position, and the additional property that, in each consecutive group of three consecutive code words, the first and third code words differ in only two adjacent coordinate positions.

Abstract: A pulse width modulator includes at least one input for receiving an input signal and pulse width modulation circuitry for generating a pulse width modulated stream and another pulse width modulated stream. The pulse width modulated stream and the another pulse width modulated stream are nominally out of phase and together represent the received input signal. A summer sums the pulse width modulated stream and the another pulse width modulated stream to generate an analog output signal.

Abstract: The present invention employs a mixture of digital signal processing and analog circuitry to reduce spurious noise in continuous time delta sigma analog-to-digital converters (CT??ADCs). Specifically, a small amount of random additive noise, also referred to as dither, is introduced into the CT??ADC to improve linear behavior by randomizing and de-correlating the quantization noise from the input signal without significantly degrading the SNR performance. In each of the embodiments, digital circuitry is used to generate the desired randomness, de-correlation, and spectral shape of the dither and simple analog circuit blocks are used to appropriately scale and inject the dither into the CT??ADC loop. In one embodiment of the invention, random noise is added to the quantizer input.

Abstract: A method of generating and allocating codewords includes allocating one of two selectable codewords b1 and b2 as codeword “b” when a preceding codeword “a” and a following codeword “b” form a code stream X, in which the codewords b1 and b2 have opposite INV values which are parameters indicating whether the number of ‘1s’ contained in a codeword is an odd number or an even number. When the code stream of the preceding codeword “a” and the following codeword b1 is X1, and when the code stream of the preceding codeword “a” and the following codeword b2 is X2, the codewords are allocated such that the INV values of X1 and X2 are maintained to be opposite when the preceding codeword “a” or the following codeword b1(b2)(b1 or b2) should be replaced by another codeword in compliance with a predetermined boundary condition given between codewords. The codewords are allocated so that a DC suppression capability of the code stream can be maintained.

Abstract: A frequency interpolating device for restoring an audio signal compressed at high ratio while keeping the high sound quality. An input digital signal to be subjected to frequency interpolation is converted to a spectrum signal representing the spectrum of the time-series signal by an analyzer. A spectrum analyzing section specifies, as an interpolating band, a deletion band not containing any spectrum among the bands defined by dividing the spectrum of the signal. A frequency interpolating section deduces the envelope of a digital signal and scales the spectrum of the spectrum distribution in the interpolating band specified by the spectrum analyzing section so that the spectrum matches with the function of the envelope and performs addition. The past spectra used for the scaling and addition are read out of a spectrum storage section. A synthesizer converts back the signal having the spectrum after the addition to the time-series signal.

Abstract: A power supply particularly suitable for high-speed optical data transmission employs readily available components to achieve desired voltage tolerances. More specifically, a voltage signal supplied to a load is converted into a digital signal and provided to a processor that derives a digital correction signal from the digital signal. The digital correction signal is then converted to an analog correction signal and is used by a feedback control circuit in the power supply to regulate the output voltage.

Abstract: Signal conversion of an input signal can be achieved by processing portions of the signal through plural parallel paths, which collectively approximate a desired infinite impulse response (IIR) filter, either alone or implemented with other signal processing functions. In one aspect, each of the paths can perform filtering, noise-shaping and/or quantization on a respective portion of the input signal to provide a corresponding representation of the respective portion of the input signal, for example, a coarser representation at a higher data rate. The corresponding representations from the parallel paths can be aggregated and further processed in a desired manner, such as conversion to an analog signal.

Abstract: An integrated circuit includes an input pad for receiving an externally generated analog signal, and a pre-sampling circuit for pre-sampling at least one internally generated analog reference signal. An analog-to-digital converter is connected to the input pad for providing a numerical value of the externally generated analog signal, and is connected to the pre-sampling circuit for providing a numerical value of the internally generated analog reference signal. A fault signaling circuit is connected to the pre-sampling circuit and to the analog-to-digital converter for generating a fault signal when the numerical value of the externally generated analog signal is equal to the numerical value of the internally generated analog reference signal. The fault signal indicates that an electrical connection providing the externally generated analog signal to the input pad is faulty.

Abstract: The present invention provides a fast data converter for decoding compressed image data. This is accomplished by using a series of parallel and serial computational steps to decompress the compressed image data and reduce processing cycle time. The high speed decoder receives the input data stream including first and second parameters having initial values and which are representative of properties of the data stream, and a third parameter having a value which is representative of a decoding property of the decoder. The decoder then decodes the initial values of the first, second, and third parameters to determine updated values of the first and second parameters by using a combination of parallel and serial processing steps. The decoder then compares the determined value of the reference parameter with the computed first subtraction value and outputs updated values for the first and second parameters based on the outcome of the comparison by the comparator to reduce decoding cycle time.

Abstract: System of multi-channel shared resistor-string digital-to-analog converters comprises a time-sharing interpolator converting the multi-channel digital audio input at low sample rate to the multi-channel digital audio output at high sample rate, a time-sharing sigma-delta modulator modulating the multi-channel digital audio input with a long sample wordlength from the interpolator to be a multi-channel digital audio output with a shorter sample wordlength, multi-channel shared resistor-string digital-to-analog converters converting the multi-channel digital audio input to be a multi-channel staircase analog signal output, and one low-order RC filter for each channel further attenuating the out-of-band noise in the analog staircase analog output, especially the high-frequency residue images.

Abstract: A system method, and apparatus for decoding a bitstream comprising variable length coded symbols are presented herein. The bitstream is parsed and the symbols that are decoded are extracted from the bitstream. The symbols that are not decoded in the parse are stored in a register. When the register is full, the contents therein are stored in the next available data word in the memory. In the foregoing manner, the bitstream without the decoded symbols is stored continuously in memory, even where the width of the memory is substantially wider than the variable length symbols.

Abstract: An arithmetic decoding apparatus is provided that carries out complete pipeline processing. Fluctuations in the pipeline caused by occurrence of the normalization are resolved by using a future-predicted Qe memory. In coding multi-valued images, common contexts are generated without distinguishing between AC and DC components of DCT coefficients.

Abstract: An input/output buffer. An input/output circuit is composed of a first PMOS transistor and a first NMOS transistor, has an I/O port coupled to an I/O pad, and a N-well region. An N-well control circuit controls the voltage level at the N-well region of the first PMOS transistor according to input signals at the I/O pad. A P-gate control circuit receives a second gate control signal and outputs to the gate of the first PMOS transistor. The P-gate control circuit is composed of a transmission gate and a third PMOS transistor. The transmission gate and the third PMOS transistor do not have to follow the design rule for ESD, and the wafer area required for the P-gate control circuit can be decreased because the P-gate control circuit is not directly connected to the I/O pad.

Abstract: An operational amplifier, a sub A/D converter, a D/A converter, and an operation amplifier in a first stage circuit operate in response to a clock signal. An operation amplifier, a sub A/D converter, a D/A converter, and an operation amplifier in a second stage circuit operate in response to a clock signal having a frequency three times as high as that of the first clock signal. An analog signal output from the operational amplifier in the first stage is applied to an input node in the second stage circuit through a switch. An analog signal output from an operational amplifier in the second stage circuit is applied to an input node in the second stage circuit through a switch.

Abstract: A method for decoding a bitstream of reversible variable length codewords parses the bitstream to extract a next reversible variable length codeword, transcodes each codeword into a pseudo-variable length codeword and decodes pseudo-variable length codeword. The transcoding produces at least some pseudo-variable length codewords suitable for leading zero lookup table decoding in specially adapted hardware. The transcoding may differ for reversible variable length codewords with initial “0” and initial “1”. These differing transcodings are decoded with may be decoded with a common lookup table or different sets of lookup tables.

Abstract: A pipeline array includes a register, a pipeline clock input, and Narrow Pulse Triggered Latches (NPTL) stages connected in series. Each NPTL stage includes a Latch Pulse Generator (LPG) and a parallel set of single latches clocked by the LPG. The latches provide the parallel data input and the parallel data output of the stage. Each LPG provides a narrow latch clock pulse in response to a Pipeline Clock Pulse (PCP) supplied to the register and the last stage of latches. Each PCP arrives at each preceding LPG in the array after a delay provided by intervening time delay units. The delays increase for each preceding stage with the least delay at the penultimate stage and with the greatest delay at the first stage. The data input of the first stage is connected to the output of the register. The data input of the each of other stage is connected to the data output of the preceding stage in the array.

Abstract: A sequential comparison type AD converter comprising series resistors for generating at respective connection portions reference values to convert an analog value to an m-bit digital value; a comparator for sequentially comparing the analog value and one of the reference value and outputting a digital value; a plurality of capacitive elements for distributing any one of the reference values by capacitance ratio; and a control unit for switching a value compared to the analog value by the comparator from a reference value to a distribution value of the plurality of capacitive elements when the comparator outputs an m-bit digital value, wherein the analog value is converted to an (m+n) bit digital value.