Abstract: A method and circuit for improving linearity of a folding or flash analog-digital-converter (ADC) circuit. Averaging resistors connect outputs of each of a bank of first pre-amplifiers. A series adjustment resistor is placed between each node connecting the output of a first bank pre-amplifier and the associated averaging resistor, and the input of each of a second bank pre-amplifier. An adjustment current is injected through the adjustment resistor during a calibration. A permanent value for adjustment current is determined such that an effect of offset errors is substantially minimized.

Abstract: A conversion method for converting a unipolar voltage data stream into a carrier-suppressed return-to-zero (CSRZ) optical data stream includes modulating a continuous optical wave with an encoded nonreturn-to-zero (NRZ) voltage data stream for providing a CSRZ optical data stream of full-width at half-maximum (FWHM) pulse width less than one-half of the transition time of the encoded nonreturn-to-zero (NRZ) voltage data stream between logical states for a reduced pulse width. The modulating circuit is either a duobinary modulator driven with a swing of ±2V? or an optical time domain multiplexed plurality of nonreturn-to-zero (NRZ) modulators with phase shifting and differential encoding.

Abstract: A method for controlling in closed loop an analog system generating an output signal from a control signal, wherein the control signal is a series of digital values, each new digital value being determined based on the difference between a signal linked to the output signal and the last determined value of the control signal multiplied by a selected factor. The present invention also relates to a device for controlling an analog system generating an analog output signal.

Abstract: A system (e.g., a digital-to-analog converter (DAC)) includes a digital section and an analog section. The digital section has a driver portion that generates drive signals based on received respective digital input signals. The drive signals are received at respective switches in the analog section. The driver portion includes logic gates that are used to generate the drive signals, such that a rise and fall time of complementary pairs of drive signals are substantially equal. The driver portion can optionally include an acceleration system to accelerate the rise and fall times of the drive signals. The switches generate respective analog signals from the drive signals.

Abstract: An extraction method and an integrated cell for extracting a binary value based on a propagation of an edge of a triggering signal in two electric paths, including across two voltage supply terminals: two parallel branches each including, in series, a resistor for differentiating the electric paths; a read transistor, the junction point of the resistor and of the read transistor of each branch defining an output terminal of the cell, and the gate of the read transistor of each branch being connected to the output terminal of the other branch; and a selection transistor.

Abstract: An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.

Abstract: A Turbo multi-user detector (MUD) processing system in multiple access communications channels that decreases the likelihood of improper decoding of the final values of interest, thereby allowing for a reduction in the number of iterations performed and lowers complexity without negatively impacting performance. The present invention comprises a multi-user detector serially concatenated to two decoder sections in such a manner that data flows iteratively from the MUD and to each detector stage and back to the MUD to correct for errors.

Abstract: A digital-to-analog converter generates an output voltage according to an input code. The converter includes: a plurality of positive current sources, a plurality of negative current sources, an assistant current source, and a control logic. The control logic converts the input code to a plurality of positive control bits and negative control bits for respectively controlling the positive current sources and the negative current sources so a current can be provided to a resistor for achieving the purpose of to establishing the required output voltage. The assistant current source also provides current to the resistor when the negative current sources provide current. When the input code is a 2s complement negative number, the control logic simply codes a 1s complement number to generate the negative control bits according to the input code such that the converter provides a negative output voltage according to the negative input code and the assistant current source.

Abstract: A conversion system converts an input signal from a digital signal to an analog signal over an extended dynamic range. The system includes a DAC system and a mode selector. The mode selector selects a mode of operation for the digital-to-analog converter system from a plurality of modes. The mode selector selects a mode according to a characteristic of the input signal. Each of the modes is associated with an instantaneous dynamic range and quantization noise level of the DAC system. The ensemble of modes provides an improvement in total or effective dynamic range compared to any DAC component within the DAC system.

Abstract: The present invention relates to all-optical OR and XOR logic elements employing saturable absorbers as optical gates. Saturable absorbers are arranged in paths of the Mach-Zehnder interferometer, respectively. If the total power of an input optical signal and a continuous wave signal is higher than a transparent input power of the saturable absorbers, the input optical signal passes through the saturable absorbers, and then the optical signals through the two paths are combined, so that it is possible to obtain the operational characteristics of the OR and XOR logic elements. According to the present invention, unlike the optical logic element using a cross-phase modulation by a semiconductor optical amplifier, phase difference depending upon the input optical power is not generated between two paths, so that it is possible to alleviate a restriction of an allowable range of the input optical power.

Abstract: Pulse width modulation systems and methods are described. In one aspect, a pulse width modulation system includes a register and a code word generator. The code word generator has an input for receiving a specified output frequency and a specified duty cycle and is operable to generate code words of different lengths. The code word generator is operable to generate a base code word having a length set to achieve the specified output frequency and having a thermometer code value set in accordance with the specified duty cycle. The code word generator is further operable to load the register with a code word pattern including a sequence of one or more copies of the base code word.

Abstract: A method and circuit for terminating a pre-amplification array for stable linearity of a folding or flash analog-digital-converter (ADC) circuit over a temperature range. Termination resistors with pre-selected temperature coefficients are coupled between outputs of a first and a last amplifier of an amplifier bank in an averaged pre-amplification stage and a termination voltage source. The termination resistors and the termination voltage provide a current that compensates temperature dependent changes in the current flowing from other amplifiers outputs towards the output of the first and last amplifiers stabilizing linearity when temperature changes. Multiple termination resistors with different temperature coefficients may be employed to better approximate the desired temperature coefficient for optimum performance.

Abstract: A method is used for reducing spikes in a digital-to-analog converter (DAC), which includes a plurality of digit circuits for transforming a digital voltage signal into an analog voltage signal. The method includes receiving the digital voltage signal, setting the digit circuit corresponding to a predetermined bit of the digital voltage signal closest to an output module, and outputting an analog voltage signal corresponding to the digital voltage signal, wherein the predetermined bit of the digital voltage signal is the bit with least signal variation among the bits of the digital voltage signal.

Abstract: A bandpass filter for a radio-frequency signal comprises an input section for a signal to be filtered, an output section for the filtered signal and at least one resonator electromagnetically or directly coupled to input and output sections. The shape of the resonator has binary rotation symmetry and/or mirror symmetry with respect to a signal propagation direction and is adapted to be excited into an oscillation having the same type of symmetry by applying the signal to be filtered to the input section.

Abstract: A method and apparatus of processing waveforms acquired in a waveform digitizing instrument utilizing multiple, interleaved digitizing elements is provided to improve the accuracy of the data acquired is provided. The present method utilizes measured analog-to-digital converter frequency response characteristics to generate sets of coefficients. When data is acquired by a waveform digitizing system, the present method utilizes these coefficients to correct the waveform, thus undoing the adverse effects of the non-ideal frequency response characteristics, resulting in a waveform acquired with higher fidelity. The waveform resulting from this method is a waveform that more closely represents the signal sampled by the digitizing system.

Abstract: System and methods are provided for selective noise generation. A delta-sigma modulator receives digital input and produces a digital output. A digital-to-analog converter converts the digital output into an analog output. The analog output comprises quasi-random noise having at least one low noise frequency band. The low noise frequency bands have respective associated shapes and center frequencies. A frequency control controls the delta-sigma modulator to alter one of the respective center frequency and the shape of the at least one low noise frequency band.

Abstract: The present invention relates to a coding apparatus for encoding data represented by 8 bit input symbols into 12 bit output codes for serially transmitting the codes along a communication channel, the codes being represented in the channel by signals having a limited minimum and maximum pulse width and sampled by a receiver at each receiver's clock period. The invention reduces artifacts introduced by sending data at a higher payload rate than the bandwidth of the communication channel, such as the voltage and current offsets introduced in the data at the receiver as a function of the preceding data.

Abstract: An apparatus for generating quadrature phase signals in a half-rate data recovery circuit, which is adapted to generate a first and a second clock signals having the same frequency and being 90 degrees out of phase with each other. The apparatus for generating quadrature phase signals mainly comprises a base selector, a first phase interpolator and a second phase interpolator. The base selector generates, based on a region control signal, a pair of phase region boundaries for the first clock signal as well as a pair of phase region boundaries for the second clock signal by using a plurality of reference clock signals. The first and second phase interpolators perform, based on a position control signal, weighted average processes for the two pairs of phase region boundaries, respectively, to thereby obtain the first and the second clock signals.

Abstract: An interleaving A/D conversion type waveform digitizer module comprising a means for eliminating spurious components resulting from phase errors according to N A/D converters, wherein the digitizer samples signals continually with a predetermined timing corresponding to a interleaving configuration of the A/D converters, receives signals outputted by a tested device to be tested, converts the signals into digital signals, performs Fourier-transform of the digital signals and performs interleaving.

Abstract: Techniques are described for analog-to-digital signal conversion. According to exemplary embodiments, a first request is associated with a plurality of input terminals and a second request is associated with one of the input terminals. An analog signal presented at each of a portion of the input terminals associated with the first request is converted in succession into a digital value until the one of the input terminals associated with the second request is reached. A predetermined amount of time is waited to receive the second request. An analog signal presented at each of a remaining portion of the input terminals associated with the first request is converted in succession into a digital value when one of an expiration of the predetermined amount of time and a receiving of the second request occurs.