Abstract: A system (e.g., a digital-to-analog converter (DAC)) includes a digital section and an analog section. The digital section has drivers that generate drive signals based on received digital input signals. The drive signals are received at switches in the analog section of the DAC. The switches generate analog signals therefrom. Swing values of the drive signals are limited to a predetermined amount to substantially eliminate glitch in the analog signals. The drivers can be coupled between first and second nodes that receive different power signal values. Controlling the power signal values allows for the limiting of the swing values. Limiting the swing values limits stored charged in the first and second switches, which substantially eliminates glitch in the analog signals. This can be done regardless on environmental variances (e.g., temperature variance) during operation of the DAC.

Abstract: A method and apparatus for system offset calibration using an overranging ADC is provided. The overranging ADC is configured to convert an analog signal into an intermediary digital signal. The conversion range of the overranging ADC is extended beyond the full dynamic range of the ADC system. The intermediary digital signal has more bits than the digital output signal. A digital fine offset adjustment circuit is configured to provide the digital output signal by digitally subtracting a fine offset from the intermediary digital signal and decoding the intermediary digital signal. The digital output signal has approximately no offset, and has approximately no loss in dynamic range.

Abstract: A low weight encoding circuit of a power delivery system for encoding data sent out on an I/O bus with minimal current drawn so as to minimize signal and timing distortions. Such a low weight encoding circuit comprises a current balance tester arranged to test whether a predetermined number of data bits is current balanced; a current balance encoder and decode bit generator arranged to encode data bits and generate encoded data and corresponding decode bits if the predetermined number of data bits is not current balanced; and a latch arranged to latch either the data bits, via an I/O bus, if said predetermined number of data bits is current balanced or the encoded data and corresponding decode bits, via the I/O bus, if the predetermined number of data bits is not current balanced.

Abstract: A method for the design of tunable filters is disclosed. MEMS switches are used to alter the resonant frequency of one or more resonators. By tuning the resonant frequency of the resonators, the filter's characteristics also are tuned. Furthermore, MEMS switches are used to alter the input coupling, including direct input coupling and capacitive input coupling. Direct input coupling is altered by using the MEMS switches to select different input connection points. Capacitive input coupling is altered by using MEMS switches to add additional input capacitance to an input coupling capacitor.

Abstract: In the prior art, it has been difficult to provide a data generator and a data generating method which serve to implement an efficient transmitter, as well as a transmitter utilizing this data generator. The present invention provides a raw data generator that generates, from an inputted signal, an I signal and a Q signal which are orthogonal to each other and an amplitude component of a quadrature signal composed of the I and Q signals, a delta sigma modulator that delta-sigma-modulates the amplitude component, a first multiplier that outputs first data obtained by multiplexing normalized I data obtained by dividing the I signal by the amplitude component, by the delta-sigma-modulated signal, and a second multiplier that outputs second data obtained by multiplexing normalized Q data obtained by dividing the Q signal by the amplitude component, by the delta-sigma-modulated signal.

Abstract: A surface acoustic wave filter unit having three interdigital transducers arranged along the surface acoustic wave propagation direction is disposed on a piezoelectric substrate. An unbalanced signal terminal and balanced signal terminals are provided for the surface acoustic wave filter unit. At least one of the three interdigital transducers is out of phase relative to the other interdigital transducers. Reflectors are arranged so as to sandwich the three interdigital transducers therebetween. The reflectors are grounded. Thus, a surface acoustic wave filter having a balance-to-unbalance conversion function and having high balance between the balanced signal terminals is achieved.

Abstract: A decoding apparatus using a precharging scheme is provided, where the size of an IC is minimized. The decoding apparatus may be used in a resistance array digital/analog converting apparatus implemented in an IC for driving a TFT-LCD to minimize the size of the IC. The disclosed decoding apparatus includes an input device for inputting digital data signals, a precharge device for precharging a plurality of output nodes with a first logic value in response to a precharge signal before the plurality of output nodes are enabled by a digital data signal provided from the input device, and a switch device for providing a second logic value to an output node from among the plurality of output nodes.

Abstract: An offset-difference coding process for data encoding and decoding wherein for each of the paired input data, the encoding process first determines the greater of the two input data, then calculates the difference between the two input data, replaces the larger input data with the calculated difference, and encodes the calculated difference and the smaller input data. The offset-difference coding process also generates an indicator if the larger input data that is replaced by the calculated difference is not statistically larger than the smaller input data.

Abstract: A semiconductor device, for use in a semiconductor memory device, for controlling a core voltage generator for providing a core voltage to be coupled to a bit line sensing amplifier, comprises a bit line sensing start signal controller for receiving a bit line sensing start signal to generate a delayed bit line sensing start control signal in response to a refresh signal; a core overdriving controller for generating an overdriving control signal in response to the delayed bit line sensing start signal; and a core voltage generator for generating the core voltage in response to the delayed bit line sensing start signal and the overdriving control signal to thereby provide core voltage to the bit line sensing amplifier after a predetermined delayed time from the bit line sensing start control signal.

Abstract: Disclosed herein is a feed-through filter having improved shielding and mounting functions. The feed-through filter of the present invention has an insulating substrate (40), one or more lead terminal through holes (42), lead terminal connection parts (43a), a top surface ground part (41), filter devices (C1 and C2), and a bottom surface ground part (44). The insulating substrate (40) has top, bottom and side surfaces. The lead terminal through holes (42) pass through the top and bottom surfaces of the insulating substrate (40). The lead terminal connection parts (43a) are separately formed around the through holes (42) on the top surface using conductive materials, and electrically connected to lead terminals (L1 and L2). The top surface ground part (41) is formed along the border of the top surface of the insulating substrate (40).

Abstract: A circuit (100) is adapted for use in a radio frequency receiver and includes a transconductance amplifier (110), a direct digital frequency synthesizer (130), and a digital-to-analog converter (DAC) (120). The transconductance amplifier (110) has an input terminal for receiving a radio frequency signal, and an output terminal for providing a current signal. The direct digital frequency synthesizer (130) has an output terminal for providing a digital local oscillator signal at a selected frequency. The DAC (120) has a first input terminal coupled to the output terminal of the transconductance amplifier (110), a second input terminal coupled to the output terminal of the direct digital frequency synthesizer (130), and an output terminal for providing an output signal.

Abstract: Numerous embodiments for a method of performing Huffman decoding are disclosed.

Abstract: A system and method provide deglitch filtering. The system has a voltage-based deglitching filter and timing-based deglitching filter. The voltage-based deglitching filter connects with the timing-based deglitch filter, such that the output of the voltage-based deglitch filter connects to the input of the timing-based deglitch filter. The voltage-based deglitch filter is in feedback with the timing based deglitching filter.

Abstract: The invention relates to a method for converting a digital signal an analogue signal and to a digital to analogue converter comprising means for converting a digital signal to a thermometer coded signal, means for randomizing the thermometer coded signal, means for controlling the means for randomizing based on the digital signal and means for converting the randomized signal to analogue.

Abstract: A D/A conversion circuit in accordance with the present invention, which is provided with a switch swD, allows a writing operation of a voltage (a true gradation voltage) to be performed at a higher speed by first applying a first voltage (a voltage close to the true gradation voltage), which is supplied without passing through a resistor element, to an output line and then applying a second voltage (the true gradation voltage), which is supplied via the resistor element, to the output line. Thus, the present invention can provide a D/A conversion circuit capable of writing display data to liquid crystal cells with higher precision at higher speed, and a semiconductor device utilizing such a D/A conversion circuit.

Abstract: A receiving apparatus and a receiving method for receiving a signal modulated by a multi-carrier modulation scheme for transmitting the information code using a plurality of carriers. The signal contains data carriers and regularly-inserted pilot carriers fixed in amplitude and phase. The cross-correlation between the received signals with the data carriers distant to such an extent as to eliminate the correlation with each other is calculated, and based on the result of the cross-correlating operation by the correlating operation unit, the signal correlation component as related to the pilot carriers is extracted.

Abstract: Binary words are converted between a non-encoded format and a compressed encoded format, in which the binary words are, at least in part, represented by encoded bit sequences that are shorter than the respective binary word in the non-encoded format. The shortest encoded bit sequences are selected according to the statistical recurrence of the respective words in the non-encoded format, and associated with the binary words with higher recurrence are encoded bit sequences comprising bit numbers that are accordingly smaller. The correspondence between binary words in non-encoded format and the encoded bit sequences associated to them is established by means of indices of an encoding vocabulary. The conversion process includes: arranging the indices in an ordered sequence; organizing the sequence into groups of vectors; splitting each group into a given number of vectors; and encoding the vectors independently from one another.

Abstract: A method quantizes an input signal of N samples into a string of k symbols drawn from a q-ary alphabet. A complementary method reproduces a minimally distorted version of the input signal from the quantized string, given some distortion measure. First, an [N,k]q linear error-correcting code that has a sparse generator factor graph representation is selected. A fixed mapping from q-ary symbols to samples is selected. A soft-input decoder and an encoder for the SGFG codes is selected. A cost function is determined from the input signal and a distortion measure, using the fixed mapping. The decoder determines an information block corresponding to a code word of the SGFG code with a low cost for the input signal. The input signal can be reproduced using the encoder for the SGFG code, in combination with the fixed mapping.

Abstract: A longitudinally coupled resonator type surface acoustic wave element including three interdigital electrode portions is disposed on a piezoelectric substrate. The surface acoustic wave device is constructed so that balance-unbalance conversion can be carried out by using two surface acoustic wave elements, and the input/output impedances are different from each other by about four times. The interdigital pitches in the surface acoustic wave elements are set so as to be different from each other. Alternatively, one-terminal-pair surface acoustic wave resonators are connected in series with at least ones of the input and output sides of the surface acoustic wave elements, the interdigital electrode finger pitches of the one-terminal-pair surface acoustic wave resonators provided on the right and left sides are set to be different from each other.

Abstract: A position detection apparatus including a detection unit for an absolute track including a plural number of ABS heads for absolute track, in which the separation between neighboring heads is broadened. The n ABS heads 10-1 to 10-n are arrayed to satisfy the following equations 1 and 2 when n is an even number and the following equations 1 and 3 when n is an odd number: &lgr;1=m&lgr;, m being an integer not less than 2  (1) &lgr;1≠k(2n/2+1)&lgr;, k being a natural number  (2) &lgr;1≠k(2n+1)&lgr;  (3). By arraying the ABS heads 10-1 to 10-n under these conditions, the separation between neighboring ones of the ABS heads 10-1 to 10-n can be 2&lgr; or larger.