Abstract: Managing a primary bit stream involves converting a qB/rB encoded bit stream to an xB/yB encoded bit stream and multiplexing an additional bit stream with the xB/yB encoded bit stream at a transmission side of a link. The additional bit stream is then demultiplexed from the xB/yB encoded bit stream and the xB/yB encoded bit stream is converted back to the qB/rB encoded bit stream at the receiver side of the link. The qB/rB encoded bit stream is converted to and from the xB/yB encoded bit stream so that the additional bit stream can be multiplexed with the qB/rB encoded bit stream using multiplexing/demultiplexing systems that are compatible with the xB/yB multiplexing system. In an application, a 4B/5B encoded bit stream is converted to an 8B/10B encoded bit stream and an additional bit stream is multiplexed with the 10B code-words of the 8B/10B encoded bit stream using code-word manipulation.

Abstract: An apparatus and method for signal processing in a root-mean-square (RMS) meter. In representative embodiments, the root-mean-square (RMS) meter includes an RMS converter having a converter input and a converter output. The RMS converter converts a time varying signal applied to the converter input to a signal at the converter output. The value of the signal at the converter output is indicative of the RMS value of the applied signal. The signal at the converter output comprises a non-time varying component and a time varying component as determined by a time constant of the RMS converter. The RMS meter further includes an inverting amplifier having an inverter input and an inverter output. The converter output is connected to the inverter input. In addition, the RMS meter includes a switch having first, second, and central contacts. The converter output is connected to the first contact, and the inverter output is connected to the second contact.

Abstract: A data shuffler apparatus shuffles input bits to perform dynamic element matching. The shuffler apparatus includes N input shufflers, each input shuffler having N input terminals and N output terminals, each input terminal of each input shuffler receiving a respective one of the input bits. The apparatus also includes N output shufflers, each output shuffler having N input terminals and N output terminals, the input and output shufflers being interconnected such that each of the N output terminals of each input shuffler is connected to a respective input terminal of a different one of the N output shufflers.

Abstract: An amplifier is provided having an electrically conductive structure. The structure has a waveguide network disposed in an inner region thereof. The network has an input section and an output section. The conductive structure has an amplifier input port and amplifier output port formed in outer wall portions of such structure. The network also includes a plurality of amplifier module input ports disposed in an outer surface of the structure. The amplifier input ports are coupled to the amplifier port through the input section of the network. The network further includes a plurality of amplifier module output ports disposed in said outer surface of the structure. The amplifier module output ports are coupled to the amplifier output port through the output section of the network. Each one of the amplifier module output ports is associated with one of the plurality of amplifier module input ports. The amplifier includes a plurality of amplifier modules.

Abstract: A sigma-delta programmer is supplied with a data word having a word length of N bits. The most significant L bits of the data word represent the places before the decimal point, and the remaining N−L less significant bits represent the places after the decimal point in the data word. A sigma-delta modulator is supplied with the N−L+1 less significant bits of the data word. An adder receives the L−1 most significant bits of the data word and a data word that is output by the sigma-delta modulator, and outputs a signal, which is multiplied by the value two by a multiplier.

Abstract: A decimation filter in which a coefficient word length of a last-stage FIR filter is shorter than that which attains a necessary attenuation rate, and an interpolation filter in which a coefficient word length of a first-stage FIR filter is the same. The coefficient is arranged such that a region in which attenuation is insufficient is caused intensively around a Nyquist frequency. The attenuation in such a region relative to the first or last-stage FIR filter is enhanced so as to ensure sufficient attenuation, by its preceding or following FIR filter. As a result, sufficient attenuation is maintained in an inhibition region while maintaining a relatively small circuit size.

Abstract: The present invention provides a serial/parallel A/D converter which is capable of performing a high-speed and high-accuracy operation even in the case where an analog input voltage Vin greatly varies in a period between a previous sampling period in which the analog input voltage is held and the next sampling period, when converting the analog input voltage Vin input into a digital value. This serial/parallel A/D converter includes a lower-order reference voltage initializing circuit 8 for initializing a lower-order reference voltage to an initialization voltage Vrc 23.

Abstract: A filter structure (900, 1300, 1400, 1610) comprises a filter section (900) having at least two branches (901, 902) connected in parallel. A first branch (901) of said at least two branches comprises a first plurality (921, 701) of piezoelectric resonators connected in series, and a second branch (902) of said at least two branches comprises a second plurality (922, 702) of piezoelectric resonators and phase shifting means (910) connected in series. The phase shifting means are arranged to provide a phase shift of substantially 180 degrees.

Abstract: The power consumption of interconnects starts to have a significant impact on a system's total power consumption. Besides increasing buses (length, width) etc. this is mostly due to deep sub-micron effects where coupling capacitances between bus lines (wire-to-wire) are in the same order of magnitude as the base capacitances (wire-to-metal-layer). At that point, encoding schemes that solely address the minimization of transitions for the purpose of power reduction do not effectively work any more. Using a physical bus model that accurately models coupling capacitances, a signal bus encoding/decoding apparatus with encoding schemes that are partially adaptive and that take coupling effects into consideration is presented. The encoding schemes do not assume any a priori knowledge that is particular to a specific application.

Abstract: An A/D converter includes a capacitor type D/A conversion circuit including a capacitor array constituted of a plurality of capacitors for sampling an input potential and storing electric charge, a first resistor type D/A conversion circuit for generating a desired potential by potential division, a second resistor type D/A conversion circuit for generating a desired potential by potential division, a first signal path for adding an output of the first resistor type D/A conversion circuit to an output of the capacitor type D/A conversion circuit by capacity coupling; a second signal path for adding an output of the second resistor type D/A conversion circuit to an output of the capacitor type D/A conversion circuit by capacity coupling, and a comparing circuit for determining whether an output potential of the capacitor type D/A conversion circuit is higher or lower than an input potential, and thereby the circuit with processing time of A/D conversion being shortened can be provided.

Abstract: A frequency synthesizer comprising a phase-locked loop (10) and comprising: a frequency divider (14) having integral dividing ratios, a sigma-delta modulator (30) connected to the frequency divider for obtaining a resulting mean dividing ratio having a fractional component, the modulator having an input for an adjusting instruction, and at least a frequency divider (100) having a fixed fractional dividing ratio, and means (120, 40) for activating the divider having a fractional dividing ratio when the fractional component (k) of the mean dividing ratio is contained in at least a given value range, and for modifying the adjusting instruction in corresponding manner.

Abstract: A sharp-cutoff VHF elliptic filter includes a folded signal path and internally coupled feedback in a conductive enclosure. Sized for the power requirements of commercial television broadcast transmission, the filter implements the elliptic filter equation through use of cavities, resonators, and couplers. The negative feedback required by the elliptic filter equation is implemented by folding the RF signal path and coupling the feedback energy through a gap in an internal septum to sum negatively with the signal in the main signal path. The elliptic filter can have an interdigital configuration, which puts successive resonators on opposite walls of the enclosure and couples the signal at half-wavelength spacing. The elliptic filter can alternatively have a comb line configuration, which places all resonators on one wall and employs full-wavelength spacing.

Abstract: A digital input is 8-fold oversampled, delay circuits 11−1 to 11−4 and multipliers/adders 12 to 15 perform a convolution arithmetic while multipliers/adders 4 to 10 process the oversampling data into predetermined digital basic waveforms, and continuous interpolation values can be obtained, thereby requiring no low pass filter which causes deterioration of phase characteristics, and suppressing an interpolation abortion error by setting finite interpolating functions. Furthermore, by obtaining apart of oversampling data as input data by using an AND gate 2, a subsequent process using the digital basic waveform and the convolution arithmetic can be performed in a very simple process.

Abstract: The present invention provides a dielectric resonator, a dielectric filter, a dielectric duplexer capable of reducing leakage of electromagnetic waves and capable of being miniaturized, and a communication apparatus incorporating the same. In each of the dielectric resonator and filter, inside a dielectric block, there is formed a L-shaped inner-conductor-formed hole having a bend at some point of the hole in a manner extending from an outer surface of the dielectric block to a surface perpendicular to the outer surface. An inner conductor is formed on the inner surface of the inner-conductor-formed hole. On the substantially entire outer surfaces of the dielectric block, there is disposed an outer conductor, with one end of the inner-conductor-formed hole open-circuited and the remaining end of the hole short-circuited. Around the edge of the open-circuited end there is formed an outer coupling electrode.

Abstract: An ultra wideband, frequency dependent attenuator apparatus for providing a loss which can be matched with a physically longer, given delay line, but yet which provides a much shorter time delay than the physically longer, given delay line with constant group delay. The apparatus is formed by an ordinary microstrip transmission line placed in series with an engineered lossy microstrip transmission line, with both transmission lines being placed on a substrate to effectively form a hybrid microstrip transmission line. The lossy transmission line includes resistive material placed along the opposing longitudinal edges thereof. In one embodiment, spaced apart metal tracks are formed along each strip of resistive material to provide the lossy microstrip transmission line with a desired loss characteristic.

Abstract: The invention is a mounting structure of a high-frequency wiring board in which when a pitch between a conductive connecting member connected to a high-frequency signal electrode pad of a high-frequency wiring board and a conductive connecting member connected to a ground electrode pad adjacent thereto is denoted by A and a maximum diameter of these conductive connecting members in sections parallel to the lower face of the high-frequency wiring board is denoted by B, A/B≧2 is satisfied, and a space L1 between the lower face of the high-frequency wiring board and the upper face of the external electric circuit board is one sixteenth or less of a wavelength of high-frequency signals processed by a high-frequency semiconductor element.

Abstract: Disclosed is a high-temperature superconductor low-pass filter for removing broadband harmonics in a wireless communication system. The high-temperature superconductor low-pass filter includes a coupled line section and a transmission line section, in which the coupled line section is connected in parallel with the transmission line section. The coupled line section has two microstrip open-stub type parallel stripe lines stacked on a high-temperature superconductor, and the transmission line section has one stripe line. Since the high-temperature superconductor low-pass filter has attenuation poles at a stopband, it has stopband characteristics to 7-8 times wider than a cutoff frequency. The high-temperature superconductor low-pass filter can easily remove sub-harmonics which are inevitably occurred in the wireless communication system.

Abstract: A method and apparatus for recording and reproducing information to and from an optical disk. If the size of a shortest mark is made small, a signal amplitude lowers and errors are likely to occur. In order to overcome this problem, when data of asymmetric codes is written, the length of a write mark is compensated so that the shortest mark and gap have the same length.

Abstract: A tunable analog-to-digital converter which generates samples having M-bits for use with an operating circuit. The operating circuit generates a first enable signal to instruct the analog-to-digital converter to turn on. Additionally, a sensor generates an analog signal in response to a condition. The tunable analog-to-digital converter includes a primary analog-to-digital converter which receives the analog signal and converts the analog signal to a primary digital signal upon receipt of the first enable signal. The tunable analog-to-digital converter also includes a comparator and a secondary analog-to-digital converter. The comparator compares the value of the primary digital signal to a predetermined value and generates a second enable signal depending on the value of the primary digital signal and the predetermined value. The secondary analog-to-digital converter receives the analog signal and converts the analog signal to a secondary digital signal upon receipt of the second enable signal.

Abstract: A current feedback amplifier is disclosed for providing a differential output based on a single-ended or differential input signal, having first and second low impedance inputs to receive first and second input signals, and first and second phase shifting systems providing first and second phase shifted input signals based on the second and first input signals. A first intermediate system provides a first intermediate signal comprising the first input signal and the first phase shifted input signal, and a second intermediate system provides a second intermediate signal comprising the second input signal and the second phase shifted input signal, wherein gains may be applied to one or more of the input and/or phase shifted signals. The amplifier further comprises first and second output buffers providing first and second differential output signals based on the first and second intermediate signals, respectively.