Abstract: Bus interface for a two-wire bus with adjustable pull-up/pull-down resistance values. A device has a bus interface for a two-wire bus comprising a first terminal and a second terminal for connection to the two-wire bus, a pull-up resistor device connected to the first terminal for a first conductor of the two-wire bus, and a pull-down resistor device connected to the second terminal for a second conductor of the two-wire bus. The pull-up resistor device is arranged to set a pull-up resistance value based on a pull-up control signal. The pull-down resistor device is arranged to set a pull-down resistance value based on a pull-down control signal.

Abstract: A building device including a circuit board having a plurality of connection points, and a microcontroller (MCU) module having a plurality of pads and a plurality of receivers, each of the plurality of pads to connect to one of the plurality of connection points of the circuit board, and each of the plurality of receivers to removably couple a pin of a plurality of pins of a microcontroller. The microcontroller configured, via an interface, to route a signal from a pin of the plurality of pins of the microcontroller to a connection point of the plurality of connection points of the circuit board, via a pad of the plurality of pads of the MCU module.

Abstract: A device applies a pre-function to an input signal to obtain an intermediate signal, wherein the pre-function has a linear section part of the input range. The device then applies a LUT including LUT entries that define a linear section and that delimit the range of the intermediate signal that corresponds to the part of the input range, resulting in an output signal that can be linearly processed through the pre-function and the LUT. The device can process a signal with positive and negative values, where one of these lies in the part of the input range that results in linear processing.

Abstract: A console information recording dongle system includes a networking device having a networking device console port, and a console information recording dongle device. The console information recording dongle device includes a dongle device console connector that is connected to the networking device console port, a storage device, and a console information recording engine that is coupled to the dongle device console connector and the storage device. The console information recording engine receives console information generated by the networking device through the dongle device console connector via the networking device console port, and stores the console information in the storage device. The console information recording dongle device may also include a dongle device console port, and may transmit the console information that was received via the dongle device console connector through the dongle device console port.

Abstract: A power supply system for an add-in card is provided. The system includes a motherboard device mounted on a host device, a baseboard management controller configured on the motherboard device, and a microcontroller unit configured on the add-in card, the add-in card is configured on the host device, and the baseboard management controller is connected to the microcontroller unit via a system management bus; the power supply system is configured to control the microcontroller unit to send working voltage parameters for the add-in card to the baseboard management controller when the host device carrying the motherboard device is not turned on; and the baseboard management controller is configured to receive the working voltage parameters and select a power supply type for the add-in card, and control the motherboard device to supply power to the add-in card based on the power supply type when the host device is turned on.

Abstract: A circuit system includes a processing circuit, an accelerator circuit, and a buffer circuit that stores packets of data and that is coupled to the processing circuit and to the accelerator circuit. The buffer circuit functions as a crossbar circuit by allowing each of the accelerator circuit and the processing circuit to access at least one of the packets of data stored in the buffer circuit during access to another one of the packets of data stored in the buffer circuit.

Abstract: A peripheral device workspace cloud orchestrator executing at an information handling system may comprise a hardware processor executing code instructions to define user experience categories for existing peripheral device workspaces identified by peripheral device workspace identification value and a list of peripheral devices operatively at identified locations coupled to user information handling systems acting as anchor nodes for the existing peripheral device workspace and to recommend setup, for each of the user experience categories, a number of reconfigured peripheral device workspaces needed to handle execution of user workloads for all enterprise users based on previously received telemetry measurements for each of the user information handling systems, wherein each of the user experience categories includes a telemetry reading describing a user workload pattern for an anchor node and a combination of peripheral device functional capabilities for the existing peripheral device workspace for handling

Abstract: A system and method of handling interrupts in a symmetric multiprocessing system is disclosed. The symmetric multiprocessing system may comprise a plurality of ARM processors, such as Cortex-M processors. All of the possible interrupt sources are routed to all of the processing units. A message handling unit (MHU) is used to communicate between processing units to relay information about the interrupts. A MHU interrupt service routine is used to handle the enabling and disabling of the various interrupt sources, as requested by the other processing unit. The MHU interrupt service routine also tracks whether the interrupt that is to be disabled is currently executing.

Abstract: The present disclosure relates to a network port circuit which uses transceiver modules and which function according to various protocols and at various bit rates. The transceiver module having a low bit rate is connected in parallel with all two-wire ports. The transceiver modules which function according to a second network protocol and at a higher data rate are individually assigned to the individual two-wire ports. Independently of the activation of the individual transceiver modules, a voltage source is active for supplying power to the two-wire buses connected to the dual-wire ports.

Abstract: Disclosed herein is an apparatus and method for controlling nonvolatile memory. The apparatus may include nonvolatile memory and a memory controller for issuing a serial clock (SCK) to the nonvolatile memory and transferring data corresponding to a requested command to the nonvolatile memory or receiving data corresponding to a requested command from the nonvolatile memory and outputting the data to the outside through a serial-in or a serial-out in response to a read request or a write request.

Abstract: A neural processing unit (NPU) includes a controller including a scheduler, the controller configured to receive from a compiler a machine code of an artificial neural network (ANN) including a fusion ANN, the machine code including data locality information of the fusion ANN, and receive heterogeneous sensor data from a plurality of sensors corresponding to the fusion ANN; at least one processing element configured to perform fusion operations of the fusion ANN including a convolution operation and at least one special function operation; a special function unit (SFU) configured to perform a special function operation of the fusion ANN; and an on-chip memory configured to store operation data of the fusion ANN, wherein the scheduler is configured to control the at least one processing element and the on-chip memory such that all operations of the fusion ANN are processed in a predetermined sequence according to the data locality information.

Abstract: An information handling system, comprising of a BMC, an I/O device, and a BIOS. The BIOS is configured to perform an I/O health check of the I/O device of the information handling system, gather I/O health check data from the I/O health check performed, and determine a health status of the information handling system according to a set of criteria and based on the I/O health check data.

Abstract: The present disclosure belongs to the technical field of computers, in particular relates to a novel computer architecture system and a control method therefor. The computer architecture system includes a host, wherein the host includes a CPU master control unit, an EC unit, a first interface unit and a battery; the EC unit is electrically connected to the CPU master control unit and the first interface unit, respectively; and the battery is electrically connected to the CPU master control unit.

Abstract: A method includes asserting a field of an event flag mask register configured to inhibit an event handler. The method also includes, responsive to an event that corresponds to the field of the event flag mask register being triggered: asserting a field of an event flag register associated with the event; and based the field in the event flag register being asserted, taking an action by a task being executed by the data processor core.

Abstract: A peripheral device includes two or more peripheral-bus modules, a coherent interconnect, and two or more tunnel adapters coupled between the peripheral-bus modules and the coherent interconnect. The peripheral-bus modules are to exchange peripheral-bus packets with one another in accordance with a peripheral-bus protocol. The coherent interconnect is to connect electronic components of the peripheral device in accordance with a coherent interconnect protocol. The tunnel adapters are to convey the peripheral-bus packets between the peripheral-bus modules over the coherent interconnect, by translating between the peripheral-bus packets and messages of the coherent interconnect protocol.

Abstract: The present invention relates to an improved router data device of roadway equipment that mainly provides all roadway equipment with functions to receive and record the return data transmitted from roadway equipment, such as vehicle detector, changeable message sign, automatic vehicle identification, traffic signal controller, electronic tag and other devices within a specific area, through such an improved router data device that uploads the return traffic data to a management platform center side for analyzing the state of the roadway equipment. The present invention provides effective security monitoring on the roadway equipment, increases the availability and maintenance efficiency of the roadway equipment.

Abstract: An integrated circuit is described. This integrated circuit may include: a receive circuit, coupled to a segment of a LIN bus, that receives bits; a measurement circuit, coupled to the receive circuit, that measures: a rising-edge time and a falling-edge time in the bits, or a bit time and a second bit time in the bits; control logic, coupled to the measurement circuit, that compares the rising-edge time and the falling-edge time, or the bit time and the second bit time; a transmit circuit, coupled to the receive circuit, that transmits the bits on a second segment of the LIN bus; and a delay circuit, coupled to the control logic, that applies, based at least in part on the comparison, a delay to: one or more rising edges or falling edges in the bits; or one or more bit times or second bit times in the bits.

Abstract: A switch device and an operation method thereof are provided. The switch device is disposed on a motherboard, and the motherboard is suitable for connecting to a graphics card. The switch device includes a control module and a switch module. The control module receives a first signal and a second signal and generates a first control signal and a second control signal according to the first signal and the second signal. The switch module is connected to a first pin, a second pin, a third pin, and the control module. The switch device receives the first control signal and the second control signal, and switches a connection among the first pin, the second pin, and the third pin according to the first control signal and the second control signal. The first pin and the second pin are suitable for connecting to the graphics card.

Abstract: An information processing method for an information processing apparatus including an application configured to extend a function provided by a print data generation software for generating print data to be printed by a plurality of printing devices includes obtaining information about a printing device connected to the information processing apparatus, and causing a display to display, in a case where the obtained information indicates a certain type printing device, information based on a type of the certain type printing device.

Abstract: A board for CXL data transmission, a method for data transmission control and a device are provided. The board for CXL data transmission includes: a control chip, where the control chip is a chip that supports an open interconnection standard CXL protocol, and uplink ports and downlink ports are deployed on the control chip; the uplink ports, connected to a host, where the host is a device that supports a Peripheral Component Interconnect Express (PCIe) protocol or a device that supports the CXL protocol; and the downlink ports, connected to a processor at least one of and a memory module, where the downlink ports are correspondingly connected to the uplink ports, and the host is configured to transmit data to the corresponding downlink ports through the uplink ports, to transmit the data to the processor at least one of and the memory module through the downlink ports.