Abstract: A method for data transmission and a data-processing circuit are provided. The data-processing circuit includes a memory that implements a buffer and a controller for controlling an operation of the data-processing circuit. When the data-processing circuit receives input data, data-hot-bits are used to address multiple data blocks of the input data. After analyzing the data-hot-bits, a starting address and a data length of each of the data blocks can be obtained. The input data is written to the buffer according to information analyzed from the data-hot-bits, and the data-hot-bits achieve an effect of masking the dummy data address. Further, data dependency among the data blocks can be confirmed by comparing the data-hot-bits with respect to each of the data blocks before the data blocks are written to the buffer.

Abstract: A semiconductor package for skew matching in a die-to-die interface, including: a first die; a second die aligned with the first die such that each connection point of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die; and a plurality of connection paths of a substantially same length, wherein each connection path of the plurality of connection paths couples a respective connection point of the first plurality of connection points to the corresponding connection point of the second plurality of connection points.

Abstract: A bridging module, a data transmission system, and a data transmission method are provided. The bridging module obtains a first read request, and allocates a first data storage space for first return data corresponding to the first read request. The bridging module combines a first master transaction identifier and an address of the first data storage space as a first slave transaction identifier of the first read request, and sends the first read request to a slave device. The bridging module obtains a second read request, and allocates a second data storage space for second return data corresponding to the second read request. The bridging module combines a second master transaction identifier and an address of the second data storage space as a second slave transaction identifier of the second read request, and sends the second read request to the slave device.

Abstract: The present disclosure discloses example operation accelerators and compression methods. One example operation accelerator performs operations, including storing, in a first buffer, first input data. In a second buffer, weight data can be stored. A computation result is obtained by performing matrix multiplication on the first input data and the weight data by an operation circuit connected to the input buffer and the weight buffer. The computation result is compressed by a compression module to obtain compressed data. The compressed data can be stored into a memory outside the operation accelerator by a direct memory access controller (DMAC) connected to the compression module.

Abstract: An apparatus that allows for access to any and all registers of a central processing unit in a line replaceable unit (LRU) without a need to open the housing of the LRU is provided. The apparatus may receive write or read packets from an external device and relay the same to an LRU. The apparatus may receive state information from one or more registers of the LRU in response. The apparatus may transmit or transfer the state information to an external device. The apparatus may be used to update firmware in the LRU, for diagnostics or testing.

Abstract: A bus emulator device includes a first computer, a second computer, and an information interface. The first computer is configured to connect to a main bus system. The first computer includes at least write access into the information interface, and the second computer includes only read access into the information interface. In other aspects, the first computer includes only write access into the information interface, and the second computer includes at least read access into the information interface.

Abstract: The technology described herein is directed towards reducing resource-related messages in a distributed locking system in which exclusive locks can be granted. Requests for a resource lock or range thereof received during an interval are queued, along with lock release messages. The queue is processed after the interval to update the resource state, which can result in a reduction in messages. In one example, separate lock request messages received during an interval from the same requestor for two or more consecutive resource ranges are combined, whereby a single lock grant message for the combined resource ranges is sent instead of one for each request. In another example, if in an interval a lock request for a resource/range is received before a lock release, the lock is released before the lock request message is processed. This avoids sending a lock release request message to the previous owner.

Abstract: Configurable binary circuits for use in electrical power systems may include an input/output port, a binary input subsystem for receiving a binary input signal, a binary output subsystem for transmitting a binary output signal, and a switch subsystem for selecting one of the binary input subsystem or the binary output subsystem for operation. Intelligent electronic devices (IEDs) and associated methods may include one or more configurable binary circuits.

Abstract: The present disclosure includes a control board including a switchable input/output port. The switchable I/O port may provide a switchable communication bus capable of selectively supporting one of multiple different communication protocols and may provide a switchable power bus capable of selectively conducting electrical power from one of multiple different power supplies. As such, the control board may communicatively and/or electrically couple to a wide range of devices. To that end, the control board may support the dynamic interchange and reconfiguration of devices coupled to the control board, allowing a control system including the control board greater operational flexibility.

Abstract: A system and method of docking an information handling system to an intelligent wireless fan dock comprising a docking sensor to detect a docking event, a wireless module to establish a wireless link of the intelligent wireless fan dock with the docked information handling system upon detection of a docking event and to receive a dynamic fan speed request command to adjust extended fan cooling airflow from fan dock control system operating at the docked information handling system, where the fan dock control system has determined that the docked information handling system and the intelligent wireless fan dock pairing enables an increased performance mode and altered power draw limitations for the docked information handling system relative to the information handling system in an undocked state, and increasing the extended fan cooling airflow of a cooling fan based on the dynamic fan speed request command from the docked information handling system.

Abstract: A method includes receiving, at a first computing device, a first input/output (IO) command from a first artificial intelligence processing unit (AI PU), the first IO command associated with a first AI model training operation. The method further includes receiving, at the first computing device, a second IO command from a second AI PU, the second IO command associated with a second AI model training operation. The method further includes assigning a first timestamp to the first IO command based on a first bandwidth assigned to the first AI model training operation. The method further includes assigning a second timestamp to the second IO command based on a second bandwidth assigned to the second AI model training operation.

Abstract: In certain aspects, a memory device includes a memory string including a drain select gate (DSG) transistor, a plurality of memory cells, and a source select gate (SSG) transistor, and a peripheral circuit coupled to the memory string. The peripheral circuit is configured to in response to an interrupt during a program operation on a select memory cell of the plurality of memory cells, turn on at least one of the DSG transistor or the SSG transistor. The peripheral circuit is also configured to suspend the program operation after turning on the at least one of the DSG transistor or the SSG transistor.

Abstract: A data storage device and method for lane selection based on thermal conditions are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to determine that action is needed to control a thermal state of the data storage device; and in response to determining that action is needed to control the thermal state of the data storage device, send a request to a host to reduce a number of lanes the host uses to communicate with the data storage device, wherein reducing the number of lanes reduces an amount of heat generated by the data storage device. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A control unit architecture and a method in which a communication connection takes place between at least two control units, in particular in a vehicle. The method includes receiving the data packet by the first interface controller; determining, by a data analyzer, a transmission strategy for the data packet, the transmission strategy including at least one of the following actions: rejecting the data packet, and/or sending the data packet to at least one of the second interface controllers, and/or sending the data packet to at least one of the buffer stores, and/or fragmenting the data packet and sending it to at least one of the buffer stores, and/or sending the content of the at least one buffer store to at least one of the second interface controllers; implementing the transmission strategy for the data packet.

Abstract: A circuit having multiple inputs and multiple outputs the circuit being for switching signals received at any of the inputs to any of the outputs, the circuit comprising: a first switch matrix, the first switch matrix being capable of directing signals received at the inputs of the circuit to multiple first intermediate ports; a second switch matrix, the second switch matrix being capable of directing signals received at multiple second intermediate ports to multiple third intermediate ports, the number of the second intermediate ports being less than the number of the inputs of the circuit; one or more primary bypass links, each primary bypass link being capable of coupling one or more of the first intermediate ports to a respective one or more of the outputs of the circuit independently of the second switch matrix; a first redirection layer, the first redirection layer being capable of, for each first intermediate port, directing a signal received at that first intermediate port to a primary bypass link or

Abstract: A method for providing teleportation services includes receiving, by a computing device, a first signal. The first signal indicates a request for a teleportation event between a first quantum computing system (QCS) and a second QCS. A first set of qubits is associated with the first QCS. A second set of qubits is associated with the second QCS. In response to receiving the first signal, the computing device causes an allocation of a first qubit of the first set of qubits for the teleportation event. In response to receiving the signal, the computing device causes an allocation of a second qubit of the second set of qubits for the teleportation event. The computing device receives a second signal that indicates a successful completion of the teleportation event. In response to receiving the second signal, the computing system causes a deallocation of the first qubit of the first set of qubits.

Abstract: A GENZ port structure includes a body, a plurality of high-speed input pins, a plurality of high-speed output pins, a plurality of ground pins, a power supply pin, a plurality of differential clock pins, and a plurality of parameter setting pins. The main body includes a first side and a second side. The plurality of high-speed input pins are arranged on the first side. The plurality of high-speed output pins are arranged on the second side. The plurality of ground pins are interspersed between the plurality of high-speed input pins and the plurality of output pins. The power supply pins, the plurality of differential clock pins and the plurality of parameter setting pins are respectively arranged on one of the first side or the second side. The plurality of parameter setting pins are used to adjust an internal parameter setting of the GENZ port structure.

Abstract: A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages. The command buffer IC includes a first interface circuit and one or more second interface circuits. The first interface circuit receives the one or more memory commands. The one or more second interface circuits output a pre-programmed command sequence to one or more devices separate from the command buffer IC, the pre-programmed command sequence output in response to the one or more memory commands matching a pre-programmed reference command pattern.

Abstract: A machine power system of a machine may use energy provided by one or more batteries. The machine power system may also use battery data associated with the batteries to monitor the batteries, configure electrical components to operate in association with the batteries, to provide battery information via a user interface, and/or for other operations. The machine power system may be configured to use a particular battery data format. A battery data translator receives native battery data provided by a battery, uses a translation map associated with the battery to convert the native battery data into translated battery data formatted based on the particular battery data format used by the machine power system, and provides the translated battery data to the machine power system.

Abstract: An input/output station is provided. The input/output station is for a fieldbus system with a fieldbus coupler, which has a system bus interface and a fieldbus interface. The input/output station comprising a plurality of slots for pluggable input/output devices. One or more placeholder devices are also pluggable into the plurality of slots besides the input/output devices. An empty slot is also admissible for the plurality of slots. The fieldbus coupler comprises firmware which is configured for a full configuration of the input/output station. The firmware is configured to communicate with a control station in such a way that the fieldbus coupler receives the full configuration of the input/output station as a planned target configuration from the control station. The firmware is configured to confirm a full configuration of the input/output station in an operating mode irrespective of the actual occupancy of the input/output station.