Abstract: An interrupt routing method includes receiving an incoming interrupt. The method also includes assigning the incoming interrupt to a selected processor core of a set of processor cores based on a current processor running state of each processor core of the set of processor cores. The current processor running state of each processor core indicates whether a respective processor core is running a routine preventing processing of the incoming interrupt.

Abstract: Disclosed are a data transmission method and apparatus. The method comprises: first determining a transmission duration required for transmitting data to be transmitted between a first processing unit and a second processing unit; starting timing when it is detected that the data is transmitted from the first processing unit; and then, determining a physical parameter of the first processing unit when transmitting the data based on timing duration and a transmission status of the data; and transmitting the data to the second processing unit based on the physical parameter. According to this method, when there is a transmission delay in the data, the physical parameter of the first processing unit when transmitting the data can be adjusted, and the data can be transmitted to the second processing unit based on the adjusted physical parameter.

Abstract: An operating system determining system for determining an operating system installed on a terminal to which a peripheral device is connectable, the terminal being capable of having installed at least one operating system including a first operating system configured to, in response to receiving a first signal, transmitting a second signal, includes: a transmission controller configured to cause the peripheral device to automatically transmit the first signal to the terminal in response to the peripheral device being connected to the terminal (#3); a signal determiner configured to determine whether the terminal has transmitted the second signal (#4); and an operating system determiner configured to, in response to the signal determiner determining that the terminal has transmitted the second signal, determine that the terminal has the first operating system installed (#5).

Abstract: A solid state drive having a drive aggregator and multiple component solid state drives. Different component solid state drives in solid state drive are configured with different optimizations of memory/storage operations. An address map in the solid state drive is used by the drive aggregator to host different namespaces in the component solid state drives based on optimization requirements of the namespaces and based on the optimizations of memory operations that have been implement in the component solid state drives.

Abstract: Systems and methods for managing client IHS access to components of a modular Artificial Intelligence (AI) appliance are described. In an illustrative, non-limiting embodiment, an AI appliance may include: a floor module comprising an AI accelerator; and a base module coupled to the floor module, the base module having a Systems-on-Chip (SoC) and a memory coupled to, or integrated into, the SoC, where the memory includes program instructions stored thereon that, upon execution by the SoC, cause the SoC to: establish a connection with a client IHS via a local port; and control the client IHS's access to an AI accelerator.

Abstract: A multiple drive assembly, including a first and a second storage unit; a first storage link coupled to the first storage unit; a second storage link coupled to the second storage unit; a third storage link coupled between the first and the second storage links, the third storage link coupled to a drive carrier; a LCC physically coupled to the first storage link, wherein the LCC is coupled to the first storage unit through the first storage link to place the LCC in communication with the first storage unit through the first storage link, wherein the LCC is coupled to the second storage unit through i) the connection between the first and the third storage links and ii) the connection between the third and the second storage links to place the LCC in communication with the second storage unit through the first, the second, and the third storage links.

Abstract: A method, in a communication system, carried out by a switch server comprising a programmable switch and one or more field programmable gate arrays (FPGAs) is provided. The method includes receiving information related to a flow table from an offloading server, receiving data packets, identifying a FPGA corresponding to the data packets, identifying whether the data packets match a flow entry of a flow table of the FPGA, in case that the data packets match the flow entry of the flow table, processing the data packets based on the flow entry and transmitting the processed data packet, and in case that the data packets do not match the entry of the flow table, providing the data packets to the offloading server.

Abstract: A data transfer controller for controlling transfer of a plurality of data items from a first device to a plurality of second devices includes a processor configured to transfer at least one data item of a plurality of data items that is to be transferred from the first device to the plurality of second devices, to at least one first memory, upon occurrence of a condition in which an hourly transfer volume of the plurality of data items transferred from the first device to a switch exceeds a bandwidth between the first device and the switch, and to cause the plurality of second devices to acquire the at least one data item that is stored in the at least one first memory.

Abstract: The disclosure discloses a video source transmission apparatus, a video source transmission method and a computer storage medium. The video source transmission apparatus includes: a video source acquisition module configured to capture video sources in multiple formats; a video source transmission module configured to transmit a video source; a control module connected with the video source acquisition module and the video source transmission module, the control module being configured to: obtain a video source to be transmitted from the video sources in multiple formats; buffer the video source to be transmitted in a circular queue; and control, after receiving a transmission control instruction, the video source transmission module to sequentially transmit the video source to be transmitted in the circular queue.

Abstract: A vehicle network for data communication between components of a vehicle, where the vehicle network includes: a first data bus; and at least two first switching devices, each switching device having: a first data-bus data interface for connection to the first data bus; a first component data interface for connection to one of the components of the vehicle; a connection state, in which the first data-bus data interface is connected to the first component data interface; a disconnection state, in which the first data-bus data interface is disconnected from the component data interface; a first gate input for activation of the first switching device in order to switch between the connection state and the disconnection state; a first monitoring unit, which is connected to each of the first gate inputs of the switching devices in order to activate the switching devices individually in order to switch between the states.

Abstract: There is described a system and method for tracking a tag. The system and method includes a concentrator for receiving, via a one-way Bluetooth low energy (BLE) communication, at least one data packet broadcasted by a tag during a time slot assigned to the tag and identifying the tag based on the at least one data packet. The system and method also includes a gateway in communication with the concentrator for receiving the identification of the tag from the concentrator and outputting the identification of the tag.

Abstract: A method and apparatus for configuring an ARM safe firmware applied to an ARM server. The method includes: invoking the ARM safe firmware of the ARM server, and configuring a space register for a PCI link bridge and PCI devices of hierarchies of a quantity N under the PCI link bridge, wherein the ARM safe firmware is a processor firmware of the ARM server, and N is a positive integer greater than or equal to 3; and inside the ARM safe firmware, adding AER error-identification data of all of CPUs of the ARM server.

Abstract: A DMA engine may process a work queue (WQ) configured to store work queue elements (WQEs). A processor may write a work queue element (WQE) to the WQ, the WQE including a jump_wait indicator. The DMA engine may be configured to enter a jump_pause state in response to processing the WQE and determining that the jump_wait indicator is set. The DMA engine may be configured to identify a one of the WQEs based at least in part on a jump offset in a trigger message. The DMA engine may be configured to enter a run state and to begin processing the one of the WQEs in response to receiving the trigger message. The DMA engine may be configured to transfer a block of data between a memory and a network interface in response to processing the one of the WQEs.

Abstract: An interactive data transmission method is provided. The method includes: receiving a first interactive command sent by a baseboard management controller of a target device via a first communication interface through a specified logic device, the first interactive command is configured to indicate to send an interactive command of a specified interactive type to a specified accelerator card in the set of accelerator cards; querying a command data set being prestored to obtain target command data, the command data set includes a set of command data corresponding to each accelerator card in the set of accelerator cards, and the target command data is command data of the specified interactive type corresponding to the specified accelerator card; and converting the target command data into a second interactive command through the specified logic device, and sending the second interactive command to the specified accelerator card via the second communication interface.

Abstract: Methods, devices, subsystems, systems, and techniques for managing data transmissions with selectable modes are provided. In one aspect, a computing system includes: host devices, peripheral component interconnect express (PCIe) devices, and a PCIe controller having a PCIe switch coupled between the host devices and the PCIe devices. The PCIe controller is configured to: set a mode of the PCIe switch to be a first PCIe mode using first mode data, and transmit, under the first PCIe mode, first data between a first host device and at least one of the PCIe devices, and set the mode of the PCIe switch to be a second PCIe mode using second mode data, and transmit, under the second PCIe mode, second data between the first host device and one or more first PCIe devices and third data between a second host device and one or more second PCIe devices.

Abstract: Bus interface for a two-wire bus with adjustable pull-up/pull-down resistance values. A device has a bus interface for a two-wire bus comprising a first terminal and a second terminal for connection to the two-wire bus, a pull-up resistor device connected to the first terminal for a first conductor of the two-wire bus, and a pull-down resistor device connected to the second terminal for a second conductor of the two-wire bus. The pull-up resistor device is arranged to set a pull-up resistance value based on a pull-up control signal. The pull-down resistor device is arranged to set a pull-down resistance value based on a pull-down control signal.

Abstract: A building device including a circuit board having a plurality of connection points, and a microcontroller (MCU) module having a plurality of pads and a plurality of receivers, each of the plurality of pads to connect to one of the plurality of connection points of the circuit board, and each of the plurality of receivers to removably couple a pin of a plurality of pins of a microcontroller. The microcontroller configured, via an interface, to route a signal from a pin of the plurality of pins of the microcontroller to a connection point of the plurality of connection points of the circuit board, via a pad of the plurality of pads of the MCU module.

Abstract: A device applies a pre-function to an input signal to obtain an intermediate signal, wherein the pre-function has a linear section part of the input range. The device then applies a LUT including LUT entries that define a linear section and that delimit the range of the intermediate signal that corresponds to the part of the input range, resulting in an output signal that can be linearly processed through the pre-function and the LUT. The device can process a signal with positive and negative values, where one of these lies in the part of the input range that results in linear processing.

Abstract: A console information recording dongle system includes a networking device having a networking device console port, and a console information recording dongle device. The console information recording dongle device includes a dongle device console connector that is connected to the networking device console port, a storage device, and a console information recording engine that is coupled to the dongle device console connector and the storage device. The console information recording engine receives console information generated by the networking device through the dongle device console connector via the networking device console port, and stores the console information in the storage device. The console information recording dongle device may also include a dongle device console port, and may transmit the console information that was received via the dongle device console connector through the dongle device console port.

Abstract: A power supply system for an add-in card is provided. The system includes a motherboard device mounted on a host device, a baseboard management controller configured on the motherboard device, and a microcontroller unit configured on the add-in card, the add-in card is configured on the host device, and the baseboard management controller is connected to the microcontroller unit via a system management bus; the power supply system is configured to control the microcontroller unit to send working voltage parameters for the add-in card to the baseboard management controller when the host device carrying the motherboard device is not turned on; and the baseboard management controller is configured to receive the working voltage parameters and select a power supply type for the add-in card, and control the motherboard device to supply power to the add-in card based on the power supply type when the host device is turned on.