Patents Examined by John B Roche
  • Patent number: 11030129
    Abstract: According to one general aspect, a device may include a host interface circuit configured to communicate with a host device via a data protocol that employs data messages. The device may include a storage element configured to store data in response to a data message. The host interface circuit may be configured to detect when a tunneling command is embedded within the data message; extract a tunneled message address information from the data message; retrieve, via the tunneled message address information, a tunneled message stored in a memory of the host device; and route the tunneled message to an on-board processor and/or data processing logic. The on-board processor and/or data processing logic may be configured to execute one or more instructions in response to the tunneled message.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: June 8, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ramdas P. Kachare, Zvi Guz, Son T. Pham, Anahita Shayesteh, Xuebin Yao, Oscar Prem Pinto
  • Patent number: 11023392
    Abstract: Access to a memory shared between a first interface and a second interface is arbitrated. Following a request to access the memory emanating from the second interface, while current access to the memory is granted to the first interface, a count is triggered having a maximum count time. A access to the memory is authorized for the second interface at the end of occupation of the access granted to the first interface if the end of occupation finishes before the end of the maximum count time, or otherwise at the end of the maximum count time.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: June 1, 2021
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Jean-Louis Labyre
  • Patent number: 11016790
    Abstract: State machine engines are disclosed, including those having an inter-rank bus control system, which may include a register. The state machine engine may include a plurality of configurable elements, such that each of the plurality of configurable elements comprises a plurality of memory cells. These cells may analyze data and output a result of the analysis. The IR bus control system may halt a write operation of data to be analyzed by the cells based, at least in part, on one or more conditions.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: May 25, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Brian Lewis Brown
  • Patent number: 10996975
    Abstract: Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example method includes receiving an interrupt message by a hypervisor, the interrupt message generated by a hierarchical memory component responsive to receiving a read request initiated by an input/output (I/O) device, gathering, by the hypervisor, address register access information from the hierarchical memory component, and determining, by the hypervisor, a physical location of data associated with the read request.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Anton Korzh, Vijay S. Ramesh, Richard C. Murphy
  • Patent number: 10997107
    Abstract: A system on chip includes an interconnect circuit including at least p input interfaces and at least k output interfaces, p source devices respectively coupled to the p input interfaces and k access ports respectively coupled to the k output interfaces and belonging to a target that includes one or more target devices. Each source device is configured to deliver transactions to the target via one of the access ports. An associated memory of each access port is configured to temporarily store the transactions received by the access port. The target is configured to deliver, for each access port, a fill signal representative of a current fill level of its associated memory. A control circuit is configured to receive the fill signals from the access ports and select the access ports eligible to receive a transaction depending on the current fill levels.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: May 4, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Yassine El Khourassani, Patrick Valdenaire, Emmanuel Ardichvili
  • Patent number: 10998975
    Abstract: An information flow control device has: a first network interface card on a transmission side, the first network interface card including first and second transceivers, each of the first and second transceivers having a transmit port and a receive port; and a second network interface card on a receiving side, the second network interface card including at least one receive port. A first data connection segment connects the first transceiver transmit port to the second transceiver receive port, a second data connection segment connects the second transceiver transmit port to the first transceiver receive port, and a third data connection segment connects the first transceiver transmit port to the receive port of the second network interface card. The first and second segments provide continuity, while the third segment provides one-way data transfer. The first and second transceivers are replaceable with third and fourth transceivers to provide different throughput.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: May 4, 2021
    Assignee: Controlled Interfaces, LLC
    Inventor: Jeffrey Charles Menoher
  • Patent number: 10996961
    Abstract: Systems and methods are described for modifying input and output (I/O) to an object storage service by implementing one or more owner-specified functions to I/O requests. A function can implement a data manipulation, such as filtering out sensitive data before reading or writing the data. The functions can be applied prior to implementing a request method (e.g., GET or PUT) specified within the I/O request, such that the data to which the method is applied may not match the object specified within the request. For example, a user may request to obtain (e.g., GET) a data set. The data set may be passed to a function that filters sensitive data to the data set, and the GET request method may then be applied to the output of the function. In this manner, owners of objects on an object storage service are provided with greater control of objects stored or retrieved from the service.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: May 4, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Kevin C. Miller, Ramyanshu Datta, Robert Devers Wilson, Timothy Lawrence Harris
  • Patent number: 10990548
    Abstract: A processing device, operatively coupled with a plurality of memory devices, is configured to receive a direct memory access (DMA) command for moving a plurality of data sectors from a source memory region to a destination memory region, the DMA command comprising a priority value. The processing device further assigns the DMA command to a priority queue of a plurality of priority queues based on the priority value of the DMA command, each priority queue has a corresponding set of priority values. The processing device also determines an execution rate for each priority queue of the plurality of priority queues. The processing device then executes a plurality of DMA commands from the plurality of priority queues according to the corresponding execution rate of each priority queue.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: April 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Dhawal Bavishi, Laurent Isenegger
  • Patent number: 10991436
    Abstract: Disclosed in some examples are methods, systems, memory devices, and machine-readable mediums which increase read throughput by introducing a delay prior to issuing a command to increase the chances that read commands can be executed in parallel. Upon receipt of a read command, if there are no other read commands in the command queue for a given portion (e.g., plane or plane group) of the die, the controller can delay issuing the read command for a delay period using a timer. If, during the delay period, an eligible read command is received, the delayed command and the newly received command are both issued in parallel using a multi-plane read. If no eligible read command is received during the delay period, the read command is issued after the delay period expires.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: April 27, 2021
    Assignee: Micron Technology, Inc.
    Inventor: David Aaron Palmer
  • Patent number: 10990547
    Abstract: A device includes a platform implemented, at least in part, in a static region of programmable circuitry and a dynamic region of programmable circuitry configured to implement user-specified circuitry in communication with the platform. The platform is configured to establish and maintain a first communication link with a host data processing system and a second communication link with a network while at least a portion of the dynamic region of programmable circuitry is dynamically reconfigured.
    Type: Grant
    Filed: August 11, 2019
    Date of Patent: April 27, 2021
    Assignee: Xilinx, Inc.
    Inventors: Chandrasekhar S. Thyamagondlu, Ravi Sunkavalli, Ravi N. Kurlagunda, Ellery Cochell
  • Patent number: 10983937
    Abstract: In accordance with an embodiment, a method for managing access to a bus shared by interfaces includes: when to the bus is granted to one of the interfaces, triggering a counting having a minimum counting period; and when at least one access request to the bus emanating from at least one other of the interfaces is received during the minimum counting period, releasing the access granted to the one of the interfaces, and creating an arbitration point at an end of the minimum counting period.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: April 20, 2021
    Assignees: STMICROELECTRONICS (ROUSSET) SAS, STMICROELECTRONICS SA
    Inventors: Olivier Ferrand, Daniel Olson, Anis Ben Said, Emmanuel Ardichvili
  • Patent number: 10983929
    Abstract: In an information processing device serving as a PCIe system including a host device and a plurality of memory devices, one of the plurality of memory devices is defined as a master memory. The other memory devices are defined as slave memories, and are logically coupled to the master memory. The plurality of memory devices thus constitute a single virtual storage. When accessing is performed from a root complex to the plurality of memory devices constituting the single virtual storage, the root complex hands over a bus master to the master memory. The master memory receives a command regarding the accessing from the root complex, changes address information used for the accessing in the command regarding the accessing, based on a logical relationship with the slave memories, and sends changed command regarding the accessing to the slave memories.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: April 20, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Shinji Inoue
  • Patent number: 10983933
    Abstract: A memory module includes a substrate, plural memory devices, and a buffer. The plural memory devices are organized into at least one rank, each memory device having plural banks. The buffer includes a primary interface for communicating with a memory controller and a secondary interface coupled to the plural memory devices. For each bank of each rank of memory devices, the buffer includes data buffer circuitry and address buffer circuitry. The data buffer circuitry includes first storage to store write data transferred during a bank cycle interval (tRR). The address buffer circuitry includes second storage to store address information corresponding to the data stored in the first storage.
    Type: Grant
    Filed: April 4, 2020
    Date of Patent: April 20, 2021
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Craig E. Hampel
  • Patent number: 10983940
    Abstract: A remote technical support system includes an edge device that operates as a highly secured conduit for a technician to view, access, and control a target device via a secure protocol over a connection medium between the edge device and the target device. The edge device's architecture allows it to selectively present numerous peripheral devices to the target device. The architectural components of the edge device can be controlled by a technician through a secure connection with a trusted server which allows authorized to access the edge device. The edge device also relays technician commands to and obtains diagnostic information from the target device and communicates feedback to the technician over the secure connection. The commands may be relayed to the target via the one or more selectively connected USB peripherals.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: April 20, 2021
    Assignee: Infinity Tribe Group Inc.
    Inventors: Jeremy Lefebvre, Joseph Jonathan Stubbs, Gregory Thomas McMullin
  • Patent number: 10977199
    Abstract: A first command is received from a virtual or physical host associated with a storage system which includes two or more hosts. The first command comprises one or more physical request page (PRP) entries associated with the non-volatile memory express (NVMe) standard. The one or more PRP entries are modified with an indication of the virtual or physical host. A second command is sent with the modified one or more PRP entries to a solid state drive (SSD). A memory request is received from the SSD, where the memory request comprises the modified one or more PRP entries. The memory request is routed to the virtual or physical host based on the indication of the virtual or physical host in the modified one or more PRP entries.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: April 13, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Salil Suri, Yingdong Li, Szu-Hsien Ho
  • Patent number: 10979337
    Abstract: A method, system and computer program product are disclosed for routing data packet in a computing system comprising a multidimensional torus compute node network including a multitude of compute nodes, and an I/O node network including a plurality of I/O nodes. In one embodiment, the method comprises assigning to each of the data packets a destination address identifying one of the compute nodes; providing each of the data packets with a toio value; routing the data packets through the compute node network to the destination addresses of the data packets; and when each of the data packets reaches the destination address assigned to said each data packet, routing said each data packet to one of the I/O nodes if the toio value of said each data packet is a specified value. In one embodiment, each of the data packets is also provided with an ioreturn value used to route the data packets through the compute node network.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: April 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Dong Chen, Noel A. Eisley, Philip Heidelberger
  • Patent number: 10972408
    Abstract: Systems, apparatuses, and methods for implementing a configurable packet arbiter with minimum progress guarantees are described. An arbiter includes at least control logic, a plurality of counters, and a tunables matrix. The tunables matrix stores values for a plurality of configurable parameters for the various transaction sources of the arbiter. These parameter values determine the settings that the arbiter uses for performing arbitration. One of the parameters is a minimum progress guarantee value that specifies how many times each source should be picked per interval. The minimum progress guarantee helps to reduce arbitration-related jitter. Also, the arbiter includes a grant counter for each source. After the minimum progress guarantees are satisfied, the arbiter selects the source with the lowest grant counter among the sources with packets eligible for arbitration. Then, the arbiter increments the grant counter of the winning source by a grant increment amount specific to the source.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: April 6, 2021
    Assignee: Apple Inc.
    Inventors: Nachiappan Chidambaram Nachiappan, Vinodh R. Cuppu
  • Patent number: 10966004
    Abstract: An information flow control device has: a first network interface card on a transmission side, the first network interface card including first and second transceivers, each of the first and second transceivers having a transmit port and a receive port; and a second network interface card on a receiving side, the second network interface card including at least one receive port. A first data connection segment connects the first transceiver transmit port to the second transceiver receive port, a second data connection segment connects the second transceiver transmit port to the first transceiver receive port, and a third data connection segment connects the first transceiver transmit port to the receive port of the second network interface card. Interconnection of the first and second transceivers provides continuity while connection of the first transceiver transmit port and the receive port of the second network interface card enables hardware-enforced one-way data transfer.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: March 30, 2021
    Assignee: Controlled Interfaces, LLC
    Inventor: Jeffrey Charles Menoher
  • Patent number: 10942884
    Abstract: The present disclosure provides a dual-edge triggered ring buffer and a communication system. The dual-edge triggered ring buffer includes a logic clock generation module and a data writing module. The logic clock generation module is configured to generate a corresponding first logic clock signal upon detecting an input of the trigger signal corresponding to the multiple first trigger signal input terminals, or to generate a corresponding second logic clock signal upon detecting an input of the trigger signal corresponding to the multiple second trigger signal input terminals. The data writing module is configured to write data output from the external system through the multiple corresponding input terminals according to the first logic clock signal or the second logic clock signal.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: March 9, 2021
    Assignee: Radiawave Technologies Co., Ltd.
    Inventors: Yigao Shao, Yulin Tan, Jon Sweat Duster, Ning Zhang, Haigang Feng
  • Patent number: 10942875
    Abstract: A method, computer program product, and computer system for monitoring host IO latency. It may be identified that a rate of the host IO latency is at a one of a plurality of levels. At least one of a rate of background IOs and a rate of host IOs may be regulated based upon, at least in part, the rate of the host IO latency being at the one of the plurality of levels.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: March 9, 2021
    Assignee: EMC IP Holding Company, LLC
    Inventors: Philippe Armangau, Vamsi Vankamamidi