Abstract: A transaction accelerator may be connected between at least one host device and a bus, and a method of operating the transaction accelerator may include receiving a first transaction request from the at least one host device, transmitting the first transaction request to the bus, and transmitting a first transaction response corresponding to the first transaction request to the at least one host device, in response to the transmitting the first transaction request to the bus.

Abstract: A Universal Serial Bus (USB) audio device kit includes a USB peripheral audio device and a passive USB-to-analog audio adapter. The USB peripheral audio device includes a USB interface configured to communicatively interface the USB audio peripheral device with a USB host device. The passive USB-to-analog audio adapter is configured to electrically interface the USB peripheral audio device with analog audio equipment via the USB interface.

Abstract: The techniques disclosed herein implement a centralized lighting module configured to control a diverse set of lighting-enabled peripheral devices. The set of lighting-enabled peripheral devices is diverse with respect to a type and a manufacturer. The lighting module is referred to as a centralized lighting module because the lighting module is part of an operating system of a computing device. Consequently, a user of the computing device no longer has to download and learn to use multiple different lighting applications if the user wants to create a diverse lighting ecosystem in which lighting-enabled peripheral devices from different manufacturers are connected to the computing device. Similarly, a developer of a computing application no longer has to engage and interact with multiple application programming interfaces (APIs) and software development kits (SDKs) if the developer wants users of their computing application to be able to create a diverse lighting ecosystem.

Abstract: An apparatus includes a communication apparatus and a second controller. The communication apparatus includes a memory to store a program, a reception buffer to save reception data, a transfer destination buffer to receive transfer reception data and a first controller to erase the reception data when the reception data are transferred to the transfer destination buffer, and execute a hardware reset of erasing the program and executing an initialization process upon detecting abnormality. The second controller checks, after transmitting the data to the communication apparatus, whether the transmitted data are saved in the reception buffer after an elapse of a predetermined period of time shorter than a period of time till the hardware reset upon occurrence of abnormality in transferring the data. The second controller causes the communication apparatus to execute a software reset when at least some proportion of the transmitted data are saved in the reception buffer.

Abstract: A direct memory access (DMA) circuit is provided. The DMA circuit may include a plurality of groups of direct memory access channels, wherein each of the groups includes at least one DMA channel and a resource usage counter configured to count an execution time in which one of the DMA channels of the group is executed, and an arbiter configured to evaluate a value of the resource usage counter of a group upon a request for execution time by one of the DMA channels of the group, and, taking into account a result of the evaluation, to assign, delay assignment, or deny execution time for using the direct memory access to one of the groups.

Abstract: A multi-bus protocol memory controller is disclosed. The memory controller utilizes shim circuits to translate between the various bus protocols used in the System on a Chip (SoC) and the bus protocol used by the memory controller. The use of shim circuits reduces the number of bridges required in the SoC and also increases performance. The memory controller is designed such that it may interface with any bus protocol, requiring only the design and inclusion of a shim circuit for that bus protocol.

Abstract: A transceiver device, communication control device, and method for a user station of a serial bus system. The transceiver device includes a first terminal for receiving a transmission signal from a communication control device, a transmission module for transmitting the transmission signal onto a bus, a reception module for receiving the signal from the bus, the reception module configured to generate a digital reception signal from the signal received from the bus, a second terminal for sending the digital reception signal to the communication control device and for receiving an operating mode changeover signal from the communication control device, and a changeover feedback block for outputting feedback regarding a changeover of the operating mode that has taken place based on the operating mode changeover signal. The changeover feedback block is configured to output the feedback to the communication control device via the second terminal and in the digital reception signal.

Abstract: The present disclosure provides a method for detecting controller area network (CAN) bus intrusion of a vehicle-mounted network based on a Gaussian mixture model-hidden Markov model (GMM-HMM), including the following steps: obtaining a normal packet of a CAN bus of a vehicle-mounted network, and counting cycles of all packets of each CAN ID based on a time sequence, that is, a time difference between two frames of packets of a same CAN ID, to form a cycle sequence as an input of an algorithm; dividing the cycle sequence of each CAN ID into a fixed length based on the algorithm, and then training a GMM-HMM for each CAN ID to obtain a likelihood probability of a normal cycle sequence; and further counting a cycle sequence of each CAN ID for a tested packet sequence, calculating, after the cycle sequence is input a model, a likelihood probability of generating the sequence, and determining whether the packet sequence is abnormal by comparing the likelihood probability with a threshold of the likelihood probabili

Abstract: A method for data transmission and a data-processing circuit are provided. The data-processing circuit includes a memory that implements a buffer and a controller for controlling an operation of the data-processing circuit. When the data-processing circuit receives input data, data-hot-bits are used to address multiple data blocks of the input data. After analyzing the data-hot-bits, a starting address and a data length of each of the data blocks can be obtained. The input data is written to the buffer according to information analyzed from the data-hot-bits, and the data-hot-bits achieve an effect of masking the dummy data address. Further, data dependency among the data blocks can be confirmed by comparing the data-hot-bits with respect to each of the data blocks before the data blocks are written to the buffer.

Abstract: The present disclosure discloses example operation accelerators and compression methods. One example operation accelerator performs operations, including storing, in a first buffer, first input data. In a second buffer, weight data can be stored. A computation result is obtained by performing matrix multiplication on the first input data and the weight data by an operation circuit connected to the input buffer and the weight buffer. The computation result is compressed by a compression module to obtain compressed data. The compressed data can be stored into a memory outside the operation accelerator by a direct memory access controller (DMAC) connected to the compression module.

Abstract: A bridging module, a data transmission system, and a data transmission method are provided. The bridging module obtains a first read request, and allocates a first data storage space for first return data corresponding to the first read request. The bridging module combines a first master transaction identifier and an address of the first data storage space as a first slave transaction identifier of the first read request, and sends the first read request to a slave device. The bridging module obtains a second read request, and allocates a second data storage space for second return data corresponding to the second read request. The bridging module combines a second master transaction identifier and an address of the second data storage space as a second slave transaction identifier of the second read request, and sends the second read request to the slave device.

Abstract: A semiconductor package for skew matching in a die-to-die interface, including: a first die; a second die aligned with the first die such that each connection point of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die; and a plurality of connection paths of a substantially same length, wherein each connection path of the plurality of connection paths couples a respective connection point of the first plurality of connection points to the corresponding connection point of the second plurality of connection points.

Abstract: An apparatus that allows for access to any and all registers of a central processing unit in a line replaceable unit (LRU) without a need to open the housing of the LRU is provided. The apparatus may receive write or read packets from an external device and relay the same to an LRU. The apparatus may receive state information from one or more registers of the LRU in response. The apparatus may transmit or transfer the state information to an external device. The apparatus may be used to update firmware in the LRU, for diagnostics or testing.

Abstract: A bus emulator device includes a first computer, a second computer, and an information interface. The first computer is configured to connect to a main bus system. The first computer includes at least write access into the information interface, and the second computer includes only read access into the information interface. In other aspects, the first computer includes only write access into the information interface, and the second computer includes at least read access into the information interface.

Abstract: The technology described herein is directed towards reducing resource-related messages in a distributed locking system in which exclusive locks can be granted. Requests for a resource lock or range thereof received during an interval are queued, along with lock release messages. The queue is processed after the interval to update the resource state, which can result in a reduction in messages. In one example, separate lock request messages received during an interval from the same requestor for two or more consecutive resource ranges are combined, whereby a single lock grant message for the combined resource ranges is sent instead of one for each request. In another example, if in an interval a lock request for a resource/range is received before a lock release, the lock is released before the lock request message is processed. This avoids sending a lock release request message to the previous owner.

Abstract: Configurable binary circuits for use in electrical power systems may include an input/output port, a binary input subsystem for receiving a binary input signal, a binary output subsystem for transmitting a binary output signal, and a switch subsystem for selecting one of the binary input subsystem or the binary output subsystem for operation. Intelligent electronic devices (IEDs) and associated methods may include one or more configurable binary circuits.

Abstract: The present disclosure includes a control board including a switchable input/output port. The switchable I/O port may provide a switchable communication bus capable of selectively supporting one of multiple different communication protocols and may provide a switchable power bus capable of selectively conducting electrical power from one of multiple different power supplies. As such, the control board may communicatively and/or electrically couple to a wide range of devices. To that end, the control board may support the dynamic interchange and reconfiguration of devices coupled to the control board, allowing a control system including the control board greater operational flexibility.

Abstract: A system and method of docking an information handling system to an intelligent wireless fan dock comprising a docking sensor to detect a docking event, a wireless module to establish a wireless link of the intelligent wireless fan dock with the docked information handling system upon detection of a docking event and to receive a dynamic fan speed request command to adjust extended fan cooling airflow from fan dock control system operating at the docked information handling system, where the fan dock control system has determined that the docked information handling system and the intelligent wireless fan dock pairing enables an increased performance mode and altered power draw limitations for the docked information handling system relative to the information handling system in an undocked state, and increasing the extended fan cooling airflow of a cooling fan based on the dynamic fan speed request command from the docked information handling system.

Abstract: A method includes receiving, at a first computing device, a first input/output (IO) command from a first artificial intelligence processing unit (AI PU), the first IO command associated with a first AI model training operation. The method further includes receiving, at the first computing device, a second IO command from a second AI PU, the second IO command associated with a second AI model training operation. The method further includes assigning a first timestamp to the first IO command based on a first bandwidth assigned to the first AI model training operation. The method further includes assigning a second timestamp to the second IO command based on a second bandwidth assigned to the second AI model training operation.

Abstract: In certain aspects, a memory device includes a memory string including a drain select gate (DSG) transistor, a plurality of memory cells, and a source select gate (SSG) transistor, and a peripheral circuit coupled to the memory string. The peripheral circuit is configured to in response to an interrupt during a program operation on a select memory cell of the plurality of memory cells, turn on at least one of the DSG transistor or the SSG transistor. The peripheral circuit is also configured to suspend the program operation after turning on the at least one of the DSG transistor or the SSG transistor.