Abstract: A GENZ port structure includes a body, a plurality of high-speed input pins, a plurality of high-speed output pins, a plurality of ground pins, a power supply pin, a plurality of differential clock pins, and a plurality of parameter setting pins. The main body includes a first side and a second side. The plurality of high-speed input pins are arranged on the first side. The plurality of high-speed output pins are arranged on the second side. The plurality of ground pins are interspersed between the plurality of high-speed input pins and the plurality of output pins. The power supply pins, the plurality of differential clock pins and the plurality of parameter setting pins are respectively arranged on one of the first side or the second side. The plurality of parameter setting pins are used to adjust an internal parameter setting of the GENZ port structure.

Abstract: A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages. The command buffer IC includes a first interface circuit and one or more second interface circuits. The first interface circuit receives the one or more memory commands. The one or more second interface circuits output a pre-programmed command sequence to one or more devices separate from the command buffer IC, the pre-programmed command sequence output in response to the one or more memory commands matching a pre-programmed reference command pattern.

Abstract: A machine power system of a machine may use energy provided by one or more batteries. The machine power system may also use battery data associated with the batteries to monitor the batteries, configure electrical components to operate in association with the batteries, to provide battery information via a user interface, and/or for other operations. The machine power system may be configured to use a particular battery data format. A battery data translator receives native battery data provided by a battery, uses a translation map associated with the battery to convert the native battery data into translated battery data formatted based on the particular battery data format used by the machine power system, and provides the translated battery data to the machine power system.

Abstract: An input/output station is provided. The input/output station is for a fieldbus system with a fieldbus coupler, which has a system bus interface and a fieldbus interface. The input/output station comprising a plurality of slots for pluggable input/output devices. One or more placeholder devices are also pluggable into the plurality of slots besides the input/output devices. An empty slot is also admissible for the plurality of slots. The fieldbus coupler comprises firmware which is configured for a full configuration of the input/output station. The firmware is configured to communicate with a control station in such a way that the fieldbus coupler receives the full configuration of the input/output station as a planned target configuration from the control station. The firmware is configured to confirm a full configuration of the input/output station in an operating mode irrespective of the actual occupancy of the input/output station.

Abstract: A direct memory access (DMA) controller, an electronic device that uses the DMA controller, and a method of operating the DMA controller are provided. The DMA controller is configured to access a memory that contains a privilege area and a normal area. The method of operating the DMA controller includes the following steps: searching for a DMA channel that is in an idle state in the DMA controller; setting a register value of a mode register of the DMA channel such that the DMA channel operates in a privilege mode; setting a memory address register and a byte count register of the DMA channel; and controlling the DMA channel to transfer data based on the memory address register and the byte count register.

Abstract: An orchestrator ensures the best available vehicle communication technology is selected. In the computer architecture, the orchestrator is injected on the data bus line is also coupled to a plurality of independent silos of vehicle communication technologies for autonomous driving vehicle technologies. Real-time accurate strength signals associated with the plurality of independent silos are received. One of the independent silos of communication is selected for rerouting the data transfer, based on a type of data involved in the data transfer, and based on a best available of the plurality of independent silos for the data transfer type. The data transfer is directed over the selected independent silo that is the best available.

Abstract: A failure recommendation system for a command line interface (CLI) uses machine learning to predict the most likely command to correct an unsuccessful or failed attempt to perform an intended operation using the CLI. The failure recommendation system is based on a conditional probability model trained on failure-success pairs of commands from CLI telemetry data to learn the most likely command to remediate a failure. The conditional probability model predicts the most likely command based on a failure type and the failed command. The failure type is identified through a failure type classifier and is used to select the most likely command to remediate a failure from the different events that may lead to a failure.

Abstract: A method for Serial Peripheral Interface (SPI) operating-mode synchronization between an SPI host and an SPI device, which communicate over an SPI bus, includes predefining, in the SPI device, one or more values on the SPI bus as indicative of lack of synchronization of an SPI operating mode between the SPI host and the SPI device. Re-synchronization of the SPI operating mode is initiated in response to receiving any of the predefined values in the SPI device.

Abstract: To reduce software development man-hours when vehicle models are developed an in-vehicle equipment controller includes a CPU and memory. The CPU has, as a software configuration, an application layer, a middleware layer, and a device driver. In the middleware layer, a first communication packet on the application side and a second communication packet on a device driver side are installed. In the middleware layer, a communication path between the application layer and the device driver is generated based on a mapping table stored in the memory.

Abstract: Techniques for intelligently routing IO to a storage class memory (SCM) namespace are disclosed. A configuration for a namespace is determined, where the configuration indicates a type of IO that the namespace is structured to handle. Details about the configuration of the namespace are stored in a repository. A forwarding rule is generated based on the namespace's stored configuration. When incoming IO having attributes similar to that type is received, implementation of the forwarding rule causes the incoming IO to be directed to the namespace. Attributes of a particular incoming IO are determined. As a result of the attributes satisfying a similarity threshold relative to the type, the forwarding rule is implemented such that the particular incoming IO is directed to the namespace.

Abstract: Disclosed herein are self-aware, self-modifying, autonomous connection mechanisms. Exemplifying intelligent systems introduce some of the embodiments of the autonomous connection mechanism techniques.

Abstract: A host electronic device that supports both Universal Serial Bus (USB) and Controller Area Network (CAN) connections is provided. When the host electronic device detects connection from a peripheral electronic device that uses the CAN protocol, the host electronic device switches to USB-C alternate mode and routes CAN signals over sideband use signals.

Abstract: A communication system includes a central, zone ECUs capable of communicating with the central ECU via a communication bus, and zone ECUs capable of communicating with the central ECU via a communication bus. The central ECU periodically transmits, to the communication buses, a count signal including a count value counted up every time the count signal is transmitted, transmits a control signal including a start count value and control content to the communication buses, and sets a transmission priority of the count signal to be higher than a transmission priority of the control signal. The zone ECUs receive the count signal and the control signal, after the control signal is received, when the count value included in the received count signal becomes equal to the start count value included in the control signal, an operation corresponding to the control content included in the control signal is started.

Abstract: A system includes a switch unit that is connected to a host connector of a computer, an embedded controller (EC) that connected to the switch unit, and a management device that includes a device connector and a microcontroller. The device connector is connected to the host connector. The microcontroller is connected to the device connector, and sends external data via the device connector to the EC. When the EC is supplied with electricity, the EC controls the switch unit to establish an electrical connection between the EC and the host connector so as to allow the EC to communicate with the microcontroller through the EC and the host connector to receive the external data from the microcontroller.

Abstract: A self-managing database system includes a metrics collector to collect metrics data from one or more databases of a computing system and an anomaly detector to analyze the metrics data and detect one or more anomalies. The system includes a causal inference engine to mark one or more nodes in a knowledge representation corresponding to the metrics data for the one or more anomalies and to determine a root cause with a highest probability of causing the one or more anomalies using the knowledge representation. The system includes a self-healing engine, to take at least one remedial action for the one or more databases in response to determination of the root cause.

Abstract: This disclosure describes system on a chip (SOC) communications that prevent direct memory access (DMA) attacks. An example SoC includes an encryption engine and a security processor. The encryption engine is configured to encrypt raw input data using a cipher key to form an encrypted payload. The security processor is configured to select the cipher key from a key store holding a plurality of cipher keys based on a channel ID describing a {source subsystem, destination subsystem} tuple for the encrypted payload, to form an encryption header that includes the channel ID, to encapsulate the encrypted payload with the encryption header that includes the channel ID to form a crypto packet, and to transmit the crypto packet to a destination SoC that is external to the SoC.

Abstract: State machine engines are disclosed, including those having an inter-rank bus control system, which may include a register. The state machine engine may include a plurality of configurable elements, such that each of the plurality of configurable elements comprises a plurality of memory cells. These cells may analyze data and output a result of the analysis. The IR bus control system may halt a write operation of data to be analyzed by the cells based, at least in part, on one or more conditions.

Abstract: Systems and methods for predictive performance indicators for storage devices are described. The data storage device may process host storage operations and maintenance operations that impact real-time performance. A performance value and corresponding threshold may be determined. Increases in maintenance operations and resulting changes in the performance value may be predicted. When the predicted change in performance value crosses the performance threshold, the host device may be notified.

Abstract: An apparatus to facilitate efficient data sharing for graphics data processing operations is disclosed. The apparatus includes a processing resource to generate a stream of instructions, an L1 cache communicably coupled to the processing resource and comprising an on-page detector circuit to determine that a set of memory requests in the stream of instructions access a same memory page; and set a marker in a first request of the set of memory requests; and arbitration circuitry communicably coupled to the L1 cache, the arbitration circuitry to route the set of memory requests to memory comprising the memory page and to, in response to receiving the first request with the marker set, remain with the processing resource to process the set of memory requests.

Abstract: During the development of Low Power Mode (LPM) (also known as L2 Mode) for DSL (Digital Subscriber Line) systems, it has become apparent that one of the most important issues is the impact on deployed legacy DSL systems. Legacy DSL systems are not capable of operating in the presence of large changes in crosstalk noise from neighbouring lines entering and exiting LPMs. For example, prior LPM methods at least do not assure that legacy lines will be protected to guarantee that no retrains will occur. These and other issues are addressed herein.