Abstract: An interrupt signal is provided to a guest operating system. A bus connected module is operationally connected with a plurality of processors via a bus attachment device. The bus attachment device receives an interrupt signal from the bus connected module with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is running using a running indicator provided by an interrupt table entry stored in a memory operationally connected with the bus attachment device. If the target processor is running, the bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly.

Abstract: According to one general aspect, a device may include a host interface circuit configured to communicate with a host device via a data protocol that employs data messages. The device may include a storage element configured to store data in response to a data message. The host interface circuit may be configured to detect when a tunneling command is embedded within the data message; extract a tunneled message address information from the data message; retrieve, via the tunneled message address information, a tunneled message stored in a memory of the host device; and route the tunneled message to an on-board processor and/or data processing logic. The on-board processor and/or data processing logic may be configured to execute one or more instructions in response to the tunneled message.

Abstract: A message-level policy implemented with for a message routing system may be used to mediate between a variety of message sources and message targets that receive and use messages. The message-level policy may allow fine grained message-by-message policy assessment that a message routing system policy may be able to provide. The message-level policy may furthermore interact with the message routing system policy to provide mechanisms to avoid accidental leakage of protected messages or spill-over to protected regions.

Abstract: A method and system configured to receive a first report from a computer peripheral device by a receiver, determine that the first report is corrupted or received at a rate slower than the first report rate, compute a current trajectory of the computer peripheral device based on one or more intervals of movement data in the first report, compute a predicted trajectory of the computer peripheral device based on the first report, compute an incremental displacement of the computer peripheral device based on the predicted trajectory. The method and system can further generate data indicative of a position or displacement of the computer peripheral device based on the predicted trajectory of the computer peripheral device and send the data indicative of a position or displacement of the computer peripheral device at an interval that is less than twice a period of the first report rate to the host computing device.

Abstract: A method for detecting an unauthorized physical access to a bus system. The method includes detecting a test level sequence in the voltage signal; constituting a binary sampled pattern by sampling the voltage signal at specified pattern times associated with the detected test level sequence, and assigning a first value if the voltage signal is above a predefined voltage threshold at the respective pattern time, and a second value if the voltage signal is not above the voltage threshold; comparing the sampled pattern with a reference pattern that is associated with the detected test level sequence and that was constituted for the test level sequence as a sampled pattern in a state of the bus system during which no unauthorized access existed; and determining that a possible unauthorized physical access exists if the reference pattern does not match the sampled pattern.

Abstract: The embodiments herein describe a 3D SmartNIC that spatially distributes compute, storage, or network functions in three dimensions using a plurality of layers. That is, unlike current SmartNIC that can perform acceleration functions in a 2D, a 3D Smart can distribute these functions across multiple stacked layers, where each layer can communicate directly or indirectly with the other layers.

Abstract: Described embodiments provide systems and methods for providing data loss prevention via an embedded browser. An interprocess communication (IPC) manager may interface with an embedded browser to control the transfer of data from a first application to a second application in accordance with a policy. The IPC manager may detect a command to store data accessed on the first application via the embedded browser and store the data onto a secure container. The secure container may be dedicated to the embedded browser. The IPC manager may subsequently detect a command to retrieve data from the secure container and to replicate the data onto the second application. The IPC manager may determine a policy to apply to the data. The policy may specify whether the data from the first application is permitted to be replicated onto the second application. The IPC manager may subsequently replicate the data on the second application.

Abstract: A system including a machine learning processing device and a memory device with microbumps is disclosed. A machine learning processing device is for performing a machine learning operation, where the machine learning processing device includes a first set of microbumps. A memory device is for storing data for the machine learning operation, where the memory device includes a second set of microbumps. The first set of microbumps of the memory device are coupled with the second set of microbumps of the machine learning processing device. The first set of microbumps of the memory device and the second set of microbumps of the machine learning processing device are to transmit the data for the machine learning operation.

Abstract: Techniques are disclosed for a hybrid undo/redo for text editing, where non-linear undo and redo operations are performed across dynamic regions in a document and linear undo and redo operations are performed within the dynamic regions in the document. In an example, the hybrid undo/redo may be achieved by maintaining respective region offset values for the dynamic regions created in a document by the edits made to the document. In operation, the respective region offset values associated with the dynamic regions can be used to negate or otherwise counteract the effect of edits made in the dynamic regions.

Abstract: An expander I/O module discovery/management system includes a secondary system chassis housing an expander I/O module coupled to a server device. The server device identifies the secondary system chassis and an expander I/O module port utilized by that server device, and then generates and transmits an expander I/O module reporting communication identifying the secondary system chassis and the expander I/O module port. A primary system chassis houses a switching I/O module coupled to the expander I/O module. The switching I/O module receives the expander I/O module reporting communication and determines that the secondary system chassis identified in the expander I/O module reporting communication is different than the primary system chassis. In response, the switching I/O module assigns a virtual slot to the expander I/O module, and assigns a virtual port associated with the virtual slot to the expander I/O module port identified in the expander I/O module reporting communication.

Abstract: Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width reduction based on throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamically configurable bus widths and frequencies.

Abstract: Aspects relate to apparatuses and methods for determining and processing dormant data records on an immutable sequential listing. An exemplary apparatus includes a processor configured to monitor a plurality of timestamps associated with a plurality of data records stored on the immutable sequential listing, where the data record includes a job resume, detect inactivity in a first data record of the plurality of data records over a predetermined time period as a function of a first timestamp of the first data record, wherein the predetermined time period may be set by the user, tag, as a function of the inactivity, the first data record as an inactive first data record, and process, as a function inactivity, the first data record, wherein processing may include adding additional data or archiving inactive data records from the immutable sequential listing.

Abstract: A remote technical support system includes an edge device that operates as a highly secured conduit for a technician to view, access, and control a target device via a secure protocol over a connection medium between the edge device and the target device. The edge device's architecture allows it to selectively present numerous peripheral devices to the target device. The architectural components of the edge device can be controlled by a technician through a secure connection with a trusted server which allows authorized to access the edge device. The edge device also relays technician commands to and obtains diagnostic information from the target device and communicates feedback to the technician over the secure connection. The commands may be relayed to the target via the one or more selectively connected USB peripherals.

Abstract: An agent control device configured to execute a plurality of agents and including a processor, the processor being configured to: request execution of each of the agents at a prescribed trigger; store an interruptibility list that stipulates interruptibility of execution for each function of a given agent being executed or for an execution status of the given agent; reference the interruptibility list in order to set permissibility information relating to executability of another one of the agents in conjunction with execution of the given agent; and perform management such that, in a case in which there is a request for execution of the other agent while the given agent is executing and the permissibility information indicates that the other agent is not executable, execution of the given agent continues without responding to the request.

Abstract: A solid state drive having a drive aggregator and multiple component solid state drives. Different component solid state drives in solid state drive are configured with different optimizations of memory/storage operations. An address map in the solid state drive is used by the drive aggregator to host different namespaces in the component solid state drives based on optimization requirements of the namespaces and based on the optimizations of memory operations that have been implement in the component solid state drives.

Abstract: A port descriptor version of a port descriptor to be obtained is selected. An indication of the port descriptor version is provided in a command to be preceded before another command used to obtain the port descriptor. The other command uses the port descriptor version to obtain the port descriptor. The port descriptor is obtained, and the port descriptor includes information relating to a port to be used in communication within the computing environment.

Abstract: Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example method includes receiving an interrupt message by a hypervisor, the interrupt message generated by a hierarchical memory component responsive to receiving a read request initiated by an input/output (I/O) device, gathering, by the hypervisor, address register access information from the hierarchical memory component, and determining, by the hypervisor, a physical location of data associated with the read request.

Abstract: A port descriptor of a selected port descriptor version is obtained. The selected port descriptor version is one port descriptor version of a plurality of port descriptor versions available for selection. The port descriptor of the selected port descriptor version includes information relating to a port of the computing environment and is configured to include technology information indicating whether the port is part of a multiple lane connector packaging. A determination is made using the port descriptor of one or more operational attributes of the port. Action is taken based on the one or more operational attributes of the port.

Abstract: Disclosed in some examples are methods, systems, memory devices, and machine-readable mediums which increase read throughput by introducing a delay prior to issuing a command to increase the chances that read commands can be executed in parallel. Upon receipt of a read command, if there are no other read commands in the command queue for a given portion (e.g., plane or plane group) of the die, the controller can delay issuing the read command for a delay period using a timer. If, during the delay period, an eligible read command is received, the delayed command and the newly received command are both issued in parallel using a multi-plane read. If no eligible read command is received during the delay period, the read command is issued after the delay period expires.

Abstract: A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages. The command buffer IC includes a first interface circuit and one or more second interface circuits. The first interface circuit receives the one or more memory commands. The one or more second interface circuits output a pre-programmed command sequence to one or more devices separate from the command buffer IC, the pre-programmed command sequence output in response to the one or more memory commands matching a pre-programmed reference command pattern.