Abstract: Methods and apparatus for controlling the distance between contact pads or leads which are to be interfaced are disclosed. According to one aspect of the present invention, an electrical package includes a body and a contact. The body includes electrical circuitry such as traces. The contact is arranged on the body, and includes a contact body and a contact feature. The contact feature is a protrusion which substantially extends from the contact body, and is arranged to come into contact with an external surface. In one embodiment, the external surface is an external contact, and the contact feature is arranged to substantially space the contact body away from the external contact.

Abstract: A circuit board includes at least one insulator layer and a plurality of conductors over which a plurality of signals is carried. A plurality of terminals is coupled to at least a subset of the plurality of conductors. A void is formed in the circuit board between at least two terminals.

Abstract: To provide high-speed, low inductance capacitive decoupling, an integrated circuit (IC) package includes capacitors positioned within the mounting region between a die and an IC package substrate. A variety of types and sizes of capacitors and substrates can be employed in a variety of geometrical arrangements. In some embodiments, capacitors are sandwiched between die terminals or bumps and the substrate conductors or pads, while in other embodiments, capacitors are positioned between bar-type conductors on the surface of the IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

Abstract: Electronic devices packaged with arrayed solder balls, leads, or pads, such as Ball Grid Array (BGA) devices, are stacked together. Each stack has a bottom adapter card with metal contacts on a top surface in an array to match the array of solder balls of a lower BGA package, and final bonding pads on a bottom surface that are soldered to an underlying motherboard or printed-circuit board (PCB). An upper BGA package has its solder balls connected to a matching array of metal contacts on a top surface of an intermediate adapter card. Metal traces on the intermediate adapter card connect to lead frame pins that wrap around the edge of the intermediate adapter card and make contact with peripheral pads on the top surface of the bottom adapter card. Lead frame pins and peripheral pads can connect several intermediate adapter cards together with one bottom adapter card.

Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.

Abstract: A passive device and a module for a transceiver are provided. The passive device for a transceiver includes a semiconductor substrate or a dielectric substrate, at least one capacitor, a dielectric layer, at least one inductor, a via hole, a metal electrode, radio frequency signal lines, and a radio frequency ground. The at least one capacitor is formed on the substrate. The dielectric layer is formed on the capacitor and the substrate. The at least one inductor is formed on the dielectric layer. The via hole penetrates through the dielectric layer. The metal electrode is formed in the via hole and electrically connects the capacitor and the inductor. The radio frequency signal lines are for the inductor and the capacitor. The radio frequency ground is formed on the substrate and isolated from the radio frequency signal lines. A reduction in the area required for mounting passive devices and modules thereof contributes to the downsizing of communication systems.

Abstract: The present invention provides devices and techniques for replacing at least one processor in a multi-processor computer system with an interposer device that maintains at least some of the input/output (“I/O”) connectivity of the replaced processor or processors. Layers of the interposer device may be configured to match the corresponding layers of the motherboard to which the processors and interposer device are attached. According to some implementations of the invention, the power system of the motherboard is altered to allow a voltage regulator that powers a link between a processor and the interposer device to also power a link between the interposer device and an I/O device.

Abstract: An apparatus and method is disclosed that allows for the arranging in a three dimensional array semiconductor chips on a circuit board. A unique chip carrier is disclosed on which any IC chip can be positioned on above the other on a circuit board. Additionally, the carrier allows for the testing of IC chips on the carrier and underneath it without having to remove the carrier and chips from the system even if they are of the BGA or CSP type. The carrier includes exposed test points to allow an on site test.

Abstract: There is described a multi-layer printed circuit board and a method of installing it. The circuit board includes a first signal layer formed on its obverse surface; a ground layer arranged at a position next to the first signal layer; an electronic power source layer arranged at a position next to the ground layer; and a second signal layer formed on its reverse surface. The first and second patterns are formed around peripheral areas of the first and second signal layers, respectively. The first ground pattern and the second ground pattern are electrically coupled to each other by plural through holes, and the multi-layer printed circuit board is installed on an electro-conductive housing in such a manner that a substantially whole area of the second ground pattern electrically contacts a mounting area of the electro-conductive housing, the mounting area being an electro-conductive area continuously coupled to the electro-conductive housing.

Abstract: An integrated circuit package and a method of manufacturing the package. A silicon chip is attached to the surface of a substrate or attached to the bottom surface of a cavity in the substrate so that the active surface of the chip is exposed. One or more build-up circuit structures are formed over the substrate. Each build-up circuit structure has at least one insulation layer, at least one patterned circuit layer and a plurality of via openings with conductive material therein so that bonding pads on the active surface of the chip connect electrically with the patterned circuit layer through the vias. To form a ball grid array package, solder balls may also be attached to the solder ball pads on the patterned circuit layer so that the bonding pads on the chip are electrically connected to an external circuit through the build-up circuit structure and the solder balls.

Abstract: A device comprising a circuit, a lead having a first end connected to the circuit and having a second end, and a deformable structure connected to the second end of the lead. The invention may be embodied on a circuit board, so that the circuit board includes a substrate and a deformable structure connected to said substrate.

Abstract: A connector is configured for insertion and removal of a digital device. The connector has contacts arranged to make electrical connection to conductors on the digital device while the digital device is inserted in the connector. A first electromagnetic coupler is connected to at least one of the contacts of the connector. The electromagnetic coupler is configured for electromagnetic coupling at an interface to a second electromagnetic coupler that is connected to a communication bus.

Abstract: Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding first and second bond pad surfaces that face toward each other. First bond pads can be positioned at least proximate to the first bond pad surface and second bond pads can be positioned at least proximate to the second bond pad surface. A package connection site can provide electrical communication between the first microfeature device and components external to the package. A wirebond can be coupled between at least one of the first bond pads and the package connection site, and an electrically conductive link can be coupled between the first microfeature device and at least one of the second bond pads of the second microfeature device. Accordingly, the first microfeature device can form a portion of an electrical link to the second microfeature device.

Abstract: In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on a main surface of a wiring substrate, and electrodes of the semiconductor chip are electrically connected by wires to electrodes of the wiring substrate. In order to make the high-frequency power amplifier module small in size, a substrate-side bonding electrode electrically connected to a wire set at a fixed reference electric potential is place at a location farther from a side of the semiconductor chip than a substrate-side output electrode electrically connected to an output wire. A substrate-side input electrode electrically connected to an input wire is located at a distance from the side of the semiconductor chip about equal to the distance from the side of the semiconductor chip to the substrate-side output electrode, or at a location farther from the side of the semiconductor chip than the substrate-side bonding electrode is.

Abstract: A circuit component built-in module of the present invention includes an insulating substrate formed of a mixture comprising 70 wt % to 95 wt % of an inorganic filler and a thermosetting resin, a plurality of wiring patterns formed on at least a principal plane of the insulating substrate, a circuit component arranged in an internal portion of the insulating substrate and electrically connected to the wiring patterns, and an inner via formed in the insulating substrate for electrically connecting the plurality of wiring patterns. Thus, a highly reliable circuit component built-in module having high-density circuit components can be obtained.

Abstract: A multi-package module comprises a plurality of stacked packages including an upper package and a lower package. Each package comprises a board having located on a first side thereof a chip installation area and a bump pad area; at least one chip disposed in the chip installation area; a plurality of redistribution patterns formed on the board and electrically connected to the chip; and a plurality of first bump pads formed in the bump pad area which are electrically connected to the redistribution patterns. The respective packages are electrically connected by connecting bump pads of the upper package to bump pads of the lower package. Further, the chip installation area of the upper and lower packages not being in vertical alignment with each other.

Abstract: A compensating advanced feature patch panel that can include removable modular or fixed electronic components located directly on the patch panel which are separately or in combination capable of providing advanced features such as device detection and power insertion. The patch panel provides communications between an insulation displacement connector (IDC) at a PD/User end, and any standard interface type using unshielded twisted pair cables, such as an RJ45 connector at a switch end at performance levels of at least category 3, 5, 5e, 6 and/or higher (e.g. 6e or 7) and equivalent performance levels by compensating for the active electronics used in providing advanced features. Compensation is achieved in part through the separation and isolation of active and communication circuit elements.

Abstract: The present invention relates to a method of manufacturing electrically conducting tracks on a transparent substrate, by screen printing with an electrically conducting paste, and to the transparent substrate provided with said tracks. According to the invention, conducting tracks are formed with a width less than or equal to 0.3 mm by applying, by screen printing, a thixotropic electrically conducting paste having a ratio of the viscosity without shear stress to the viscosity under shear stress under screen-printing conditions of at least 50 and having a silver content greater than 35% and of which at least 98% of the particles which form it have a size less than 25 ?m, by means of a screen having at least 90 threads per cm, the coating of said screen being provided with slots, the narrowest width of which is equal to 0.25 mm±0.05 mm, and by subjecting said tracks to baking.

Abstract: The design methods described enable three-dimensional integrated circuit systems in which all of the dies, in a vertically bonded stack of dies, are identical. Only one mask set and wafer type is required since a single circuit design is produced for one die in the stack and reused for all the dies with little or no modification. The system scales directly as the level of stacking is increased while incurring no extra design effort, beyond that required for the initial design.

Abstract: A compensating advanced feature patch panel that can include removable modular or fixed electronic components located directly on the patch panel which are separately or in combination capable of providing advanced features such as device detection and power insertion. The patch panel provides communications between an insulation displacement connector (IDC) at a PD/User end, and any standard interface type using unshielded twisted pair cables, such as an RJ45 connector at a switch end at performance levels of at least category 3, 5, 5e, 6 and/or higher (e.g. 6e or 7) and equivalent performance levels as required by compensating for the active electronics used in providing advanced features through the use of inductive, capacitive and reactive circuit elements to compensate for advanced feature electronics.