Patents Examined by John B. Vigushin
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Patent number: 7038142Abstract: The circuit board for mounting semiconductor elements comprises a core substrate 10 formed of a fiber reinforced metal, an insulating layer 14 formed on the core substrate 10, and an interconnection layer 20 formed on the insulating layer 14, whereby the circuit board for mounting semiconductor elements can have a thermal expansion coefficient approximate to that of silicon, and light and thin but has high rigidity.Type: GrantFiled: January 13, 2003Date of Patent: May 2, 2006Assignee: Fujitsu LimitedInventor: Tomoyuki Abe
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Patent number: 7035115Abstract: A backplane for a motor controller having a control module and one or more axis modules provides both low power and low powered signals and high power used to produce motor drive signals.Type: GrantFiled: April 11, 2003Date of Patent: April 25, 2006Assignee: Rockwell Automation Technologies, Inc.Inventor: Phillip John Walesa
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Patent number: 7035113Abstract: A multi-chip electronic package which utilizes an organic, laminate chip carrier and a plurality of semiconductor chips positioned on an upper surface of the carrier. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities.Type: GrantFiled: March 24, 2003Date of Patent: April 25, 2006Assignee: Endicott Interconnect Technologies, Inc.Inventors: Lawrence R. Fraley, Voya R. Markovich
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Patent number: 7031170Abstract: An electronic device has a plastic housing. The plastic housing has components of a height-structured metallic leadframe. The components are in a matrix form and contain contact islands and chip islands on the underside of the plastic housing. Furthermore, the electronic device has a first line structure containing height-structured interconnects on the underside of the plastic housing and a second line structure containing bonding connections which are disposed within the plastic housing.Type: GrantFiled: September 30, 2002Date of Patent: April 18, 2006Assignee: Infineon Technologies AGInventors: Frank Daeche, Franz Petter
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Patent number: 7026708Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile contacts are created by any of a variety of methods and materials. A consolidated low profile contact structure and technique is provided for use in alternative embodiments of the present invention. Multiple numbers of CSPs may be stacked in accordance with the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry that exhibit one or two or more conductive layers.Type: GrantFiled: July 11, 2003Date of Patent: April 11, 2006Assignee: Staktek Group L.P.Inventors: James W. Cady, Julian Partridge, James Douglas Wehrly, Jr., James Wilder, David L. Roper, Jeff Buchle
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Patent number: 7023707Abstract: An information handling system, e.g., computer, server or mainframe, which includes a multi-chip electronic package utilizing an organic, laminate chip carrier and a plurality of semiconductor chips positioned on an upper surface of the carrier. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities of the final system product.Type: GrantFiled: March 24, 2003Date of Patent: April 4, 2006Assignee: Endicott Interconnect Technologies, Inc.Inventors: Lawrence R. Fraley, Voya R. Markovich
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Patent number: 7016198Abstract: A multi-layer printed circuit board (PCB) routes signal traces on internal signal layer(s) and includes power planes on the two outermost layers. The outer layers are maintained at the same non-ground voltage level, and are electrically connected by a series of vias that circumscribe signal traces on the internal layer(s). With a preferred maximum spacing of one-tenth the wavelength of electromagnetic energy generated by the signal traces, the vias, together with the outer power planes, contain electromagnetic energy within the PCB. One or more of the outer planes may include a second power plane area maintained at a different voltage. The two power plane areas are connected by decoupling capacitors, located proximate underlying signal traces that traverse the two power plane areas.Type: GrantFiled: April 8, 2003Date of Patent: March 21, 2006Assignee: Lexmark International, Inc.Inventors: John Thomas Fessler, Keith Bryan Hardin, Eric Wayne Westerfield
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Patent number: 7012814Abstract: The circuit board connection structure of the invention has a first circuit board and a second circuit board bonded together with a conductive resin layer. The first circuit board has a first terminal region including a plurality of first terminal electrodes arranged in a first direction and a dummy electrode placed next to the first terminal region in the first direction. The second circuit board has a second terminal region including a plurality of second terminal electrodes arranged in the first direction. The second terminal region is placed to face the first terminal region via the conductive resin layer, and the respective second terminal electrodes are electrically connected to the corresponding first terminal electrodes. The conductive resin layer covers at least part of the dummy electrode, and the at least part of the dummy electrode covered with the conductive resin layer has a plurality of openings.Type: GrantFiled: March 18, 2003Date of Patent: March 14, 2006Assignee: Sharp Kabushiki KaishaInventors: Shinichi Sugimoto, Tsuyoshi Tamura
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Patent number: 7006359Abstract: A modular electronic assembly and a method for making a modular electronic assembly are disclosed. The subject modular electronic assembly is constructed in such a way as to maximize available surface area on printed wiring boards by incorporating pretested discrete passive elements within the body of such printed wiring boards and electrically connecting the elements in a volume-efficient manner. A modular electronic assembly constructed according to the presently disclosed subject matter is formed by arranging a plurality of diverse, pretested passive components between a plurality of copper and tacky epoxy sheets, holding the passive components in place by an epoxy resin layer and electrically connecting the components together by electrical vias penetrating the tacky epoxy layers.Type: GrantFiled: July 14, 2004Date of Patent: February 28, 2006Assignee: AVX CorporationInventors: John L. Galvagni, George Korony
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Patent number: 7002813Abstract: An arrangement which has a panel-like electrical/electronic module, such as a solar power module, and a connection unit which are electrically connected to one another. The module and the connection unit each have an essentially flat printed conductor structure with connecting sections. The printed conductor structures are situated in parallel planes. The connecting sections are rigid electrical conductor sections and are bent out from the planes of the printed conductor structures of the connection unit and the module. The connecting sections of the connection unit are situated corresponding to the arrangement of the connecting sections of the module so that for the connection unit connected to the module each connecting section of the module is electrically connected to a respective connecting section of the connection unit and these adjoin one another in one section situated in a different spatial position than that of the planes of the printed conductor structures.Type: GrantFiled: October 31, 2002Date of Patent: February 21, 2006Assignees: Leopold Kostal GmbH & Co. KG, Solarworld AGInventors: Eduard Bergmann, Herwig Rilling, Peter Westermayr, Clemens Hofbauer, Boris Klebensberger, Karsten Wambach
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Patent number: 7002812Abstract: An electronic module includes an electronic circuit board having circuit elements, signal lines connected to the circuit elements, and board terminals disposed on a terminal region, and an input board and driver circuit boards mounted on the terminal region of the electronic circuit board. Each of the driver circuit boards has input terminals and output terminals. The output terminals are electrically connected to the signal lines of the electronic circuit board. The input board has main wiring lines for transmitting signals input externally, and branch wiring lines branched from the main wiring lines. The branch wiring lines are electrically connected to the input terminals of the driver circuit boards via the board terminals of the electronic circuit board.Type: GrantFiled: September 25, 2003Date of Patent: February 21, 2006Assignee: Sharp Kabushiki KaishaInventor: Yoichiro Sakaki
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Patent number: 6998647Abstract: An infrared communication module with remote control function includes a PD chip for IrDA data, an IC chip, an LED chip for IrDA data, and an LED chip for remote control transmission that are mounted on a PWB. The PD chip, IC chip and LED chips are sealed by a resin. The resin forms a light-receiving lens for infrared communication surrounding the PD chip, a light-emitting lens for infrared communication surrounding the LED chip for IrDA data, and a light-emitting lens for remote control surrounding the LED chip for remote control transmission. Such a structure allows an infrared communication module with remote control transmission function having a structure that can prevent increase in the cost of production and a mounting space.Type: GrantFiled: February 7, 2003Date of Patent: February 14, 2006Assignee: Sharp Kabushiki KaishaInventors: Keiji Morimoto, Hiroshi Mizuno
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Patent number: 6995322Abstract: A circuitized substrate including a plurality of conductive and dielectric layers and also a plurality of conductive thru-holes therein for passing high speed signals, e.g., from one component to another mounted on the substrate. The substrate utilizes a signal routing pattern which uses the maximum length of each of the thru-holes wherever possible to thereby substantially eliminate signal loss (noise) due to thru-hole “stub” resonance. A multilayered circuitized substrate assembly using more than one circuitized substrate, an electrical assembly using a circuitized substrate and one or more electrical components, a method of making the circuitized substrate and an information handling system incorporating one or more circuitized substrate assemblies and attached components are also provided.Type: GrantFiled: September 30, 2004Date of Patent: February 7, 2006Assignee: Endicott Interconnect Technologies, Inc.Inventors: Benson Chan, John M. Lauffer
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Patent number: 6995984Abstract: The invention relates to an electronic assembly, in particular for low power consumption electric switching devices such as low power contactors, time relays or the like. In order to provide protection against input current pulses, an ohmic resistor (6) is provided in the form of a resistive layer that is applied by pressing.Type: GrantFiled: June 30, 2001Date of Patent: February 7, 2006Assignee: Moeller GmbHInventor: Gerd Schmitz
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Patent number: 6992896Abstract: A multi-chip electronic package which utilizes an organic, laminate chip carrier and a pair of semiconductor chips positioned on an upper surface of the carrier in a stacked orientation. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples one or both of the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities. The first chip, e.g., an ASIC chip, is solder bonded to the carrier while the second chip, e.g., a memory chip, is secured to the first chip's upper surface and coupled to the carrier using a plurality of wirebond connections.Type: GrantFiled: September 15, 2003Date of Patent: January 31, 2006Assignee: Endicott Interconnect Technologies, Inc.Inventors: Lawrence R. Fraley, Voya Markovich
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Patent number: 6992899Abstract: An apparatus and system, as well as fabrication methods therefor, may include a conductor attached to a carrier to bridge a contact field defined by a circuit that can be mounted to a circuit board.Type: GrantFiled: March 21, 2003Date of Patent: January 31, 2006Assignee: Intel CorporationInventors: William Alger, Gary Long, Gary Brist, Carlos Mejia
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Patent number: 6989995Abstract: Electrode lead wires for each capacitor are soldered to land patterns of a mounting plate of insulation. Spacers each having a flexible structure composed of a grid of metal lines are mounted on electrode patterns printed on a printed circuit board, and tip portions of the electrode lead wires which project from the mounting plate are stuck into the spacers to provide mechanical contact therebetween. While keeping this contact, the mounting plate is secured with bolts to the printed circuit board. This forms a capacitor mounting structure. For replacement of the capacitors, by simply loosening the bolts, the entire mounting plate including all the capacitors can be demounted from the board.Type: GrantFiled: March 13, 2003Date of Patent: January 24, 2006Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Takeshi Ito
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Patent number: 6984866Abstract: Semiconductor devices and methods for making semiconductor devices. The present invention allows a flip chip assembly to be used with an optical semiconductor device. The optical semiconductor flip chip is positioned over a hole in a PCB such that the imaging area of the optical semiconductor flip chip faces the hole. The hole allows the imaging area to be unobstructed by the PCB. Underfill material can be prevented from going into the hole by erecting a barrier on top of the PCB that surrounds the hole.Type: GrantFiled: March 17, 2003Date of Patent: January 10, 2006Assignee: National Semiconductor CorporationInventors: Shahram Mostafazadeh, Joseph O. Smith, Matthew D. Penry
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Patent number: 6985365Abstract: The system and methods describe a computer system implementing an adjustable control signal path whose length may be precisely adjusted to control timing of a control signal that propagates along the path. One such adjustable signal path has two clusters of possible signal paths. Each of the signal paths in each cluster has a length, and the overall length of the control signal path may be adjusted by selectively implementing one signal path from each of the clusters by electrically connecting that path into the electrical circuit by the selective installation of zero ohm resistors. In this way, a system designer may design several possible signal path lengths on to a motherboard or printed circuit card, and implement the path length which provides the most precise signal timing adjustment.Type: GrantFiled: September 28, 2001Date of Patent: January 10, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Jeoff M. Krontz, Christopher D. McBride
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Patent number: 6985364Abstract: A voltage converter module is formed by multi-layering a first connecting layer, a first inner wiring layer, a component built-in layer, a second inner wiring layer, a second connecting layer, and a capacitor-mounted layer, and a capacitor built-in layer with resin composite. A connecting terminal formed on a terminal surface of the first connecting layer, the first inner wiring layer, the second inner wiring layer and the capacitor-mounted layer are electrically coupled to each other through via-hole conductors. The second inner wiring layer couples a voltage converter IC to peripheral components, both being incorporated in the component built-in layer. A first capacitor and a second capacitor incorporated in the capacitor built-in layer are mounted to the capacitor-mounted layer. This structure forms a circuit, in which the first capacitor is coupled to the second capacitor, between the voltage converter IC and the grounding.Type: GrantFiled: October 4, 2002Date of Patent: January 10, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroshi Higashitani, Masaaki Hayama, Yuji Mido