Abstract: A method and apparatus that allows additional contact pads to be added to a package to support debug and test operations is disclosed. In a preferred embodiment, a circuit board apparatus includes a semiconductor package and an interposer for receiving the semiconductor package. The semiconductor package preferably includes a substrate having a matrix of conductive contact pads on both the top and bottom surfaces of the substrate. The interposer preferably includes a body having a matrix of interposer contact bumps on both the inner and outer surfaces of the body. Each interposer contact bump preferably includes a metal coating and is shaped to abut a contact pad of the semiconductor package.

Abstract: A power supply terminal that prevents damage to capacitors included in a noise filter circuit therein which may occur due to a BWB's warp or thermal stresses at soldering time. The noise filter circuit is formed on a noise filter circuit substrate, being a substrate separate from the BWB. The noise filter circuit substrate is connected conductively to part of each of press fit terminals.

Abstract: A semiconductor device including bond pads disposed proximate an edge thereof, and an overcoat layer. The overcoat layer defines notches around each of the bond pads. The overcoat layer may be formed from a photoimageable material such as a photoimageable epoxy. The invention also includes an alignment device that secures the semiconductor device perpendicularly upon a carrier substrate. The alignment device includes intermediate conductive elements which correspond to the bond pads of the semiconductor device. Upon insertion of the semiconductor device into the alignment device, the notches facilitate alignment of the bond pads with their corresponding intermediate conductive elements. The intermediate conductive elements establish an electrical connection between the semiconductor device and the carrier substrate.

Abstract: The invention provides a method for attaching a flip chip to a printed wiring board. A bumped opto-electronic or electromechanical flip chip is provided. An underfill material is applied to a first portion of the flip chip, wherein a second portion of the flip chip is free of the underfill material. The flip chip is positioned on a printed wiring board, and a bumped portion of the flip chip is heated to electrically connect the flip chip to the printed wiring board. The second portion of the flip chip remains free of the underfill material when the flip chip is electrically connected to the printed wiring board.

Abstract: Methods for producing circuit elements the resultant circuit elements, and methods for making circuits therefrom are disclosed. A precursor circuit element includes a first insulating layer with conductor thereon and an electrically conducting member or bump, protruding from the conductor, that provide a shape to one surface of the precursor circuit element. A second insulating layer, including an adhesive, is placed onto the precursor circuit element and assumes the shape of the aforementioned surface of the precursor circuit element.

Abstract: An interposer to couple a microelectronic device package to a motherboard is formed from a PCB substrate. Multiple via holes are drilled through a copper-clad PCB substrate and then coated inside with copper. The copper surface coating is etched to form multiple traces. In one embodiment, the substrate is cut through each row of via holes and between each row of via holes to produce multiple individual beam-and-trace interposers. Two or more such interposers may be affixed together to form a beam-and-trace interposer array. Alternatively, the substrate is not cut into strips, and each via hole is filled completely with a conductive material to form an array of solid conductive columns through the substrate.

Abstract: According to one embodiment, a semiconductor die is situated in a cutout section of a substrate. In one embodiment, the substrate is situated on a printed circuit board such that the semiconductor die situated in the cutout section of the substrate is also situated on a support pad on the top surface of the printed circuit board. In one embodiment, a semiconductor die bond pad on the semiconductor die is connected to a substrate bond pad on the substrate. In one embodiment, an interconnect trace on the substrate is connected to an interconnect pad on the top surface of the printed circuit board.

Abstract: A carrier substrate comprising a non-conductive substrate, one or more conductive regions on, under or within the non-conductive substrate, and a plurality of pads, selectively coupled with the conductive regions, to receive and couple with conductive elements of a component, wherein at least one pad is configured to receive and couple with two or more conductive elements of the component.

Abstract: A flexible carrier substrate assembly or module that facilitates stacking of multiple carrier substrates bearing semiconductor dice for high density electronic systems. After the dice are placed on the flexible substrate, a flexible support frame may be applied to the flexible substrate. The support frame includes conductive paths therethrough to connect to circuit traces running from the dice on the substrate to the substrate perimeter to interconnect superimposed carrier substrates. The flexible carrier substrates may be bent to a radius of any given curvature to conform to various non-planar regular and irregular surfaces. Furthermore, since the frame as well as the substrate may be flexible, multiple, flexible substrate assemblies may be stacked one on top of another wherein an upper assembly has a different radius than a lower module and any intermediate assemblies have progressively differing radii from bottom to top position.

Abstract: A method for packaging semiconductor device assemblies. An assembly is formed which includes a semiconductor die, a tape positioned over the active surface of the die, and a substrate element positioned on an opposite side of the tape from the die. Bond pads of the die are exposed through a slot formed through the tape and an aligned opening formed through the substrate element facilitate the extension of intermediate conductive elements from the bond pads and through the slot and opening, to corresponding contact areas on the substrate element. One or both ends of the slot extend beyond an outer periphery of the die to facilitate introduction of an encapsulant material into a channel or receptacles defined by the slot, opening, and active surface of the semiconductor die. Prior to encapsulation, the side of the opening of the substrate element is sealed opposite the tape with a coverlay to contain the encapsulant material within the channel or receptacle.

Abstract: An adapter or housing for a module, such as a single in-line memory module (SIMM) or the like, and method of using the same are herein disclosed where the SIMM and attached housing fit a predetermined shape SIMM socket. The housing replaces SIMM board material that would otherwise be used to help secure the SIMM to a predetermined shape SIMM socket or connector. The configuration of the housing allows a SIMM or the like to be snapped or slid and secured into the housing. If desired, an adhesive, potting material and other bonding material can be used to secure the SIMM board to the housing and/or pot the SIMM within the housing.

Abstract: The adapter couples a power module to a circuit board. An adapter embodying the present invention can be configured to allow the connection of any power module regardless of pin out to any circuit board. Signal modifying circuitry can also be added to the adapter to enhance or simply modify the signal to the end user's circuit board. The modifying circuitry can act on either the input to the adapter or the output from the adapter. At least one conductive path couples the input interconnects and the output interconnects.

Abstract: In a flexible wiring board of the present invention, a first shield film is connected to a ground wiring at the bottom of an opening in a cover film. The first shield film is connected to a second shield film via a through-hole penetrating from the surface to the rear surface of a base film. Thus, the second shield film is connected to the ground wiring via the first shield film, whereby the wiring board can be wholly shielded.

Abstract: This invention provides a circuit mounting method and a circuit mounted board which can mount semiconductor elements at a high density. A recessed portion is formed in a board, a memory IC packaged in a chip size package method (CSP) is mounted in the recessed portion, and a memory IC packaged in a thin small outline package method (TSOP) is mounted on the board to cover the recessed portion.

Abstract: In some embodiments, the invention includes a system having first and second modules and a circuit board including first and second module connectors to receive the first and second modules, respectively. A first path of conductors extends from the circuit board to the first module connector, to the first module, back to the first module connector, to the circuit board, to the second module connector and to the second module. The first path couples to chips of the first and second modules, and each of the chips include on die terminations, but only some of the chips include on die terminations that are enabled.

Abstract: A capacitor includes a controlled collapse chip connection system coupled by vias to a plurality of conductive layers embedded in a dielectric. The capacitor and a die can each be mounted on opposite surfaces of a substrate using a controlled collapse chip connection. The controlled collapse chip connection provides a large number of leads for coupling to the conductive layers of the capacitor. The large number of leads reduce the inductance in the connection. For a thin substrate, the length of the conductive material connecting the capacitor to the die is short, and the inductance and resistance of the conductive material is low. A system comprising two dies can be fabricated in a small volume using a plurality of substrates and a single controlled collapse chip connection compatible capacitor for decoupling the two dies.

Abstract: A decoupling capacitor structure and its use in a circuit board mounting an ASIC is provided. The decoupling capacitor structure is arranged so that parasitic inductance caused by the connection to the decoupling capacitor and the decoupling capacitor itself is reduced. The circuit boards include at least two voltage planes. An ASIC having active device(s) is connected to one face of the circuit board. A decoupling capacitor structure is provided having at least two conductive plates in a dielectric material and is connected directly or indirectly to the ASIC. Vias extend from the conductive plates through the dielectric material to connect to circuit board vias on a second face of the printed circuit board or to the ASIC. The decoupling capacitor vias are parallel to each other; and each via connected to one conductive plate is located adjacent a via connected to another conductive plate to minimize voltage deviation.

Abstract: A socket that secures bare and minimally packaged semiconductor devices substantially perpendicularly relative to a carrier substrate. The socket includes intermediate conductive elements and a member which moves the intermediate conductive elements between an insertion position and a biased position. After placement of the intermediate conductive elements into an insertion position, a semiconductor device may be inserted into a receptacle of the socket with minimal insertion force. Movement of the member to a biased position facilitates biasing of the intermediate conductive elements against a bond pad of the semiconductor device. The intermediate conductive elements establish an electrical connection between the semiconductor device and the carrier substrate. A first embodiment of the socket includes a member which moves transversely relative to the remainder of the socket. In a second embodiment of the socket, the member moves vertically relative to the socket body.

Abstract: The inductance of the capacitor is reduced by connecting the capacitor directly to a via. In one embodiment inductance of a capacitor is reduced by a plurality of via, the number of via greater than the number of electrical couplings from the voltage pad to the voltage plane. In one embodiment the capacitor has a ground pad of a minimum size. In another embodiment the capacitor is electrically coupled to a trace having a length reduced to minimize inductance.

Abstract: A stacked backplane assembly, including two or more backplanes or midplanes having different functionality and combined together so as to form an integral unit, is provided. The backplanes forming the assembly are manufactured with prime and secondary manufacturing holes to enable alignment, so that the resulting tolerance build-up of the assembly is similar to that of a single backplane. Connectors can be arranged on the backplanes of the assembly so that an electronic or optical card can be simultaneously plugged in to one or more of the backplanes that comprise the stacked backplane assembly. The stacked backplane assembly of the embodiments of the invention is illustrated by having power and signal backplanes and midplanes, but can be equally applied to backplanes that provide other types of functionality.