Patents Examined by John Bodnar
  • Patent number: 10804218
    Abstract: A semiconductor package includes a semiconductor chip that includes a first region and a second region spaced apart from the first region; a plurality of connection bumps disposed under the first region of the semiconductor chip; and a protection layer that covers a bottom surface of the semiconductor chip in the second region, wherein the protection layer does not cover the bottom surface of the semiconductor chip in the first region and is not disposed between the plurality of connection bumps. The semiconductor chip of the semiconductor package is protected by the protection layer.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: October 13, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Lyong Kim, Seung-Duk Baek
  • Patent number: 10804194
    Abstract: A semiconductor device comprises a peripheral circuit region provided on a first substrate and including circuit devices and a contact plug extending on the first substrate in a vertical direction; a memory cell region provided on a second substrate disposed above the first substrate and including memory cells; and a through insulating region penetrating through the second substrate on the contact plug and covering an upper surface of the contact plug.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: October 13, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gang Zhang, Kwang Soo Kim, Won Bong Jung
  • Patent number: 10804277
    Abstract: A method of fabricating a semiconductor device. A cell area and a core area is defined in a substrate. A bit line structure disposed in the cell area is provided. A gate structure disposed in the core area is provided, and a core capping film disposed on the gate structure is provided. A height of the core capping film is greater than a height of the bit line structure. A first contact film is formed on the bit line structure. A second contact film is formed on the core capping film. A mask is formed on the first contact film. An upper surface of the core capping film is exposed using the mask. The first contact film is etched until a height of the first contact film becomes less than a height of the bit line structure using an etching process. In the etching process, an etching rate for the first contact film is greater than etching rates for the bit line structure and the core capping film.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: October 13, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin A Kim, Sun Young Lee, Yong Kwan Kim, Ji Young Kim, Chang Hyun Cho
  • Patent number: 10745268
    Abstract: The present disclosure relates to a MEMS apparatus with a patterned anti-stiction layer, and an associated method of formation. The MEMS apparatus has a handle substrate defining a first bonding face and a MEMS substrate having a MEMS device and defining a second bonding face. The handle substrate is bonded to the MEMS substrate through a bonding interface with the first bonding face toward the second bonding face. An anti-stiction layer is arranged between the first and the second bonding faces without residing over the bonding interface.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuei-Sung Chang, Fei-Lung Lai, Shang-Ying Tsai, Cheng Yu Hsieh
  • Patent number: 10741723
    Abstract: A component with an geometrically adapted contact structure and a method for producing such a component are disclosed. In an embodiment a component includes a contact structure including a contiguous contact layer having a plurality of openings and being assigned to a first electrical polarity of the component and a plurality of individual contacts at least in part having different vertical heights, wherein the contacts extend in the openings throughout the contiguous contact layer, wherein the contacts are laterally spaced from each other and assigned to a second electrical polarity of the component, and wherein the contacts are arranged with respect to their different heights and their positions such that a height distribution of the contacts is adapted to a predetermined geometrically non-planar contour profile.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: August 11, 2020
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventor: Alexander F. Pfeuffer
  • Patent number: 10741672
    Abstract: A method of forming a fin field effect transistors (finFET) on a substrate includes forming a fin structure on the substrate, forming a protective layer on the fin structure, and forming a polysilicon structure on the protective layer. The method further includes modifying the polysilicon structure such that a first horizontal dimension of a first portion of the modified polysilicon structure is smaller than a second horizontal dimension of a second portion of the modified polysilicon structure. The method further includes replacing the modified polysilicon structure with a gate structure having a first horizontal dimension of a first portion of the gate structure that is smaller than a second horizontal dimension of a second portion of the gate structure.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 10741572
    Abstract: A memory stack structure including a memory film and a vertical semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulating layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulating layers, a backside blocking dielectric layer may be formed in the backside recesses and sidewalls of the memory stack structures. A metallic barrier material portion can be formed in each backside recess. A metallic material portion is formed on the metallic barrier material portion. Subsequently, a metal portion comprising a material selected from cobalt and ruthenium is formed directly on a sidewall of the metallic barrier material portion and a sidewall of the metallic material portion and an overlying insulating surface and an underlying insulating surface.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: August 11, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer Makala, Yanli Zhang, Yao-Sheng Lee
  • Patent number: 10741449
    Abstract: A semiconductor device includes a first gate stack arranged about a first nanowire and a second nanowire, the first nanowire is arranged above a second nanowire, the first nanowire is connected to a first source/drain region and a second source/drain region. A second gate stack is arranged about a third nanowire and a fourth nanowire, the third nanowire is arranged above a fourth nanowire, the third nanowire is connected to a third source/drain region and a fourth source/drain region. An insulator layer having a first thickness is arranged adjacent to the first gate stack.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: August 11, 2020
    Assignee: Tessera, Inc.
    Inventors: Kangguo Cheng, Lawrence A. Clevenger, Balasubramanian S. Pranatharthiharan, John Zhang
  • Patent number: 10734282
    Abstract: Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods are also shown that provide electromagnetic isolation to reduce noise in adjacent components.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Harold Ryan Chase, Mihir K Roy, Mathew J Manusharow, Mark Hlad
  • Patent number: 10727186
    Abstract: A power semiconductor device having a high degree of reliability even when an operable temperature of a power semiconductor element is sufficiently increased. The power semiconductor device includes: a power semiconductor element including an electrode formed on a first surface; a first stress mitigation portion connected to the electrode with a first bonding portion being interposed; and a wiring portion electrically connected to the first stress mitigation portion with a second bonding portion being interposed. A bonding strength of the first bonding portion is higher than a bonding strength of the second bonding portion.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: July 28, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinnosuke Soda, Yoshinori Yokoyama, Hiroshi Kobayashi
  • Patent number: 10707133
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon. A plurality of gate structures is over the fin, individual ones of the plurality of gate structures along a direction orthogonal to the fin and having a pair of dielectric sidewall spacers. A trench contact structure is over the fin and directly between the dielectric sidewalls spacers of a first pair of the plurality of gate structures. A contact plug is over the fin and directly between the dielectric sidewalls spacers of a second pair of the plurality of gate structures, the contact plug comprising a lower dielectric material and an upper hardmask material.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Anthony St. Amour, Michael L. Hattendorf, Christopher P. Auth
  • Patent number: 10707181
    Abstract: A semiconductor device with redistribution layers formed utilizing dummy substrates is disclosed and may include forming a first redistribution layer on a first dummy substrate, forming a second redistribution layer on a second dummy substrate, electrically connecting a semiconductor die to the first redistribution layer, electrically connecting the first redistribution layer to the second redistribution layer, and removing the dummy substrates. The first redistribution layer may be electrically connected to the second redistribution layer utilizing a conductive pillar. An encapsulant material may be formed between the first and second redistribution layers. Side portions of one of the first and second redistribution layers may be covered with encapsulant. A surface of the semiconductor die may be in contact with the second redistribution layer. The dummy substrates may be in panel form. One of the dummy substrates may be in panel form and the other in unit form.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: July 7, 2020
    Assignee: AMKOR TECHNOLOGY INC.
    Inventors: Jin Young Kim, Ji Young Chung, Doo Hyun Park, Choon Heung Lee
  • Patent number: 10699963
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate. The substrate includes a first semiconductor layer, a second semiconductor layer, and an insulating layer between the first semiconductor layer and the second semiconductor layer. The semiconductor device structure also includes a gate stack over the substrate. The semiconductor device structure further includes source and drain structures in the second semiconductor layer of the substrate. The source and drain structures are on opposite sides of the gate stack. In addition, the semiconductor device structure includes a first isolation feature in the substrate. The first isolation feature includes an insulation material and surrounds the source and drain structures. The semiconductor device structure also includes a second isolation feature in the first isolation feature. The second isolation feature includes a metal material and surrounds the source and drain structures.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Han Tsai, Po-Jen Wang, Chun-Li Wu, Ching-Hung Kao
  • Patent number: 10685886
    Abstract: A method of forming a logic device and a power device on a substrate is provided. The method includes forming a first vertical fin on a first region of the substrate and a second vertical fin on a second region of the substrate, wherein an isolation region separates the first region from the second region, forming a dielectric under-layer segment on the second vertical fin on the second region, and forming a first gate structure on the dielectric under-layer segment and second vertical fin on the second region.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: June 16, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juntao Li, Kangguo Cheng, Liying Jiang, John G. Gaudiello
  • Patent number: 10679903
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a first gate structure and a second gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure and the second gate structure into a first metal gate and a second metal gate; forming a hard mask on the first metal gate and the second metal gate; removing part of the hard mask, the second metal gate, and part of the fin-shaped structure to form a trench; and forming a dielectric layer into the trench to form a single diffusion break (SDB) structure.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: June 9, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
  • Patent number: 10676345
    Abstract: A temperature-stabilized MEMS device in which heat is generated by ohmic heating as an electric current passes through at least part of one of the structural layers of the device. Various implementation options are disclosed in which the heating occurs in a device layer (25) of the device, either in an outer frame (2) or within the area of an active structure (3), or where heating occurs within a substrate (1) or a cover (8) of the device. One application of particular relevance is a gyroscope device.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: June 9, 2020
    Assignee: Y-SENSORS LTD.
    Inventor: Yishay Netzer
  • Patent number: 10665751
    Abstract: A method of manufacturing a semiconductor light-emitting device includes: preparing a layer stack including a light-extracting layer and a light-emitting structure, the light-extracting layer having a light-extracting surface in which a rugged structure is provided, the light-emitting structure being provided on a principal surface opposite to the light-extracting surface of the light-extracting layer; forming a mask over the rugged structure in a partial region of the light-extracting surface; forming a planar surface by removing the rugged structure that is exposed without having the mask formed thereover; and singulating the layer stack by irradiating the planar surface with a laser and cutting at least the light-extracting layer at a position of the planar surface.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: May 26, 2020
    Assignee: Nikkiso Co., Ltd.
    Inventors: Noritaka Niwa, Tetsuhiko Inazu
  • Patent number: 10663816
    Abstract: Disclosed is a display device and a method of manufacturing the same, wherein an end portion of a pad provided on a first substrate is spaced apart and separated from an upper surface of the first substrate, and a connection electrode electrically connected with the pad is in contact with a lateral surface of the pad and a lower surface of the pad.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: May 26, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventors: WonJun Choi, SungLim Nam, Misun Park, Jaewoong Choi, Younghyun Kong
  • Patent number: 10658382
    Abstract: An elevationally-extending string of memory cells comprises an upper stack elevationally over a lower stack. The upper and lower stacks individually comprise vertically-alternating tiers comprising control gate material of individual charge storage field effect transistors vertically alternating with insulating material. An upper stack channel pillar extends through multiple of the vertically-alternating tiers in the upper stack and a lower stack channel pillar extends through multiple of the vertically-alternating tiers in the lower stack. Tunnel insulator, charge storage material, and control gate blocking insulator is laterally between the respective upper and lower stack channel pillars and the control gate material. A conductive interconnect comprising conductively-doped semiconductor material is elevationally between and electrically couples the upper and lower stack channel pillars together. The conductively-doped semiconductor material comprises a first conductivity-producing dopant.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: May 19, 2020
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, David Daycock, Yushi Hu, Christopher Larsen, Dimitrios Pavlopoulos
  • Patent number: 10658569
    Abstract: This method for manufacturing a lead-free niobate-system ferroelectric thin film device includes: a lower electrode film formation step of forming a lower electrode film on a substrate; a ferroelectric thin film formation step of forming a niobate-system ferroelectric thin film on the lower electrode film; an etch mask pattern formation step of forming an etch mask in a desired pattern on the niobate-system ferroelectric thin film; and a ferroelectric thin film etching step of shaping the niobate-system ferroelectric thin film into a desired fine pattern by wet etching using an etchant comprising: a predetermined chelating agent including at least one selected from EDTMP, NTMP, CyDTA, HEDP, GBMP, DTPMP, and citric acid; an aqueous alkaline solution containing an aqueous ammonia solution; and an aqueous hydrogen peroxide solution.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: May 19, 2020
    Assignees: SUMITOMO CHEMICAL COMPANY, LIMITED, KANTO KAGAKU KABUSHIKI KAISHA
    Inventors: Fumimasa Horikiri, Kenji Shibata, Kazutoshi Watanabe, Kazufumi Suenaga, Masaki Noguchi, Kenji Kuroiwa