Patents Examined by John Bodnar
  • Patent number: 11411178
    Abstract: A memory cell includes: a first electrode; a resistive material layer comprising one horizontal portion and two vertical portions that are respectively coupled to ends of the horizontal portion; and a second electrode, wherein the second electrode is partially surrounded by a top boundary of the U-shaped profile and the first electrode extends along part of a bottom boundary of the U-shaped profile.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: August 9, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh Mo, Shih-Chi Kuo
  • Patent number: 11404572
    Abstract: According to one embodiment, a semiconductor device includes an element region, an element isolation region adjacent to the element region, a gate insulating layer provided on an upper surface of the element region, and a gate electrode including a semiconductor layer, the semiconductor layer containing boron (B) and including a portion provided on the gate insulating layer, the element isolation region including an upper portion including an upper surface of the element isolation region and a lower portion including a lower surface of the element isolation region, and the upper portion of the element isolation region applying compressive stress to a portion of the element region, which is adjacent to the upper portion of the element isolation region.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: August 2, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Tadayoshi Uechi, Takashi Izumida
  • Patent number: 11387409
    Abstract: Providing for improved manufacturing of silver-based electrodes to facilitate formation of a robust metallic filament for a resistive switching device is disclosed herein. By way of example, a silver electrode can be embedded with a non-silver material to reduce surface energy of silver atoms of a silver-based conductive filament, increasing structural strength of the conductive filament within a resistive switching medium. In other embodiments, an electrode formed of a base material can include silver material to provide mobile particles for an adjacent resistive switching material. The silver material can drift or diffuse into the resistive switching material to form a structurally robust conductive filament therein.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: July 12, 2022
    Assignee: CROSSBAR, INC.
    Inventors: Sung Hyun Jo, Xianliang Liu, Fnu Atiquzzaman
  • Patent number: 11383970
    Abstract: In one example, an electronic device can comprise (a) a first substrate comprising a first encapsulant extending from the first substrate bottom side to the first substrate top side, and a first substrate interconnect extending from the substrate bottom side to the substrate top side and coated by the first encapsulant, (b) a first electronic component embedded in the first substrate and comprising a first component sidewall coated by the first encapsulant, (c) a second electronic component coupled to the first substrate top side, (d) a first internal interconnect coupling the second electronic component to the first substrate interconnect, and (e) a cover structure on the first substrate and covering the second component sidewall and the first internal interconnect. Other examples and related methods are also disclosed herein.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: July 12, 2022
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventor: Sung Jae Oh
  • Patent number: 11367684
    Abstract: Embodiments include an interconnect structure and methods of forming an interconnect structure. In an embodiment, the interconnect structure comprises a semiconductor substrate and an interlayer dielectric (ILD) over the semiconductor substrate. In an embodiment, an interconnect layer is formed over the ILD. In an embodiment, the interconnect layer comprises a first interconnect and a second interconnect. In an embodiment the interconnect structure comprises an electrically insulating plug that separates the first interconnect and the second interconnect. In an embodiment an uppermost surface of the electrically insulating plug is above an uppermost surface of the interconnect layer.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: June 21, 2022
    Assignee: Intel Corporation
    Inventors: Ehren Mannebach, Kevin Lin, Richard Vreeland
  • Patent number: 11362172
    Abstract: A method for forming non-planar capacitors of desired dimensions is disclosed. The method is based on providing a three-dimensional structure of a first material over a substrate, enclosing the structure with a second material that is sufficiently etch-selective with respect to the first material, and then performing a wet etch to remove most of the first material but not the second material, thus forming a cavity within the second material. Shape and dimensions of the cavity are comparable to those desired for the final non-planar capacitor. At least one electrode of a capacitor may then be formed within the cavity. Using the etch selectivity of the first and second materials advantageously allows applying wet etch techniques for forming high aspect ratio openings in fabricating non-planar capacitors, which is easier and more reliable than relying on dry etch techniques.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: June 14, 2022
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Sansaptak Dasgupta, Han Wui Then
  • Patent number: 11348838
    Abstract: A transistor device and a method for forming a transistor device are disclosed. The method includes: forming first regions of a first doping type and second regions of a second doping type in inner and edge regions of a semiconductor body; and forming body and source regions of transistor cells in the inner region. Forming the first and second regions includes: forming first and second implanted regions in the inner and edge regions, each first implanted region including at least dopant atoms of a first doping type and each second implanted region including at least dopant atoms of a second doping type; and diffusing the dopant atoms of both doping types in a thermal process such that dopant atoms of at least one of the first and second doping types have at least one of different diffusion rates and diffusion lengths in the inner and edge regions.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: May 31, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Ingo Muri, Daniel Tutuc
  • Patent number: 11349010
    Abstract: A method of manufacturing a Schottky barrier diode includes: forming a first well region over a substrate; forming a first dielectric layer over the first well region; patterning the first dielectric layer by reducing a first thickness of the first dielectric layer; removing the first dielectric layer to expose a surface of the first well region; and forming a conductive layer over the first well region to obtain a Schottky barrier interface. A Schottky barrier diode manufactured based on the above method is also provided.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: May 31, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Meng-Han Lin, Te-An Chen
  • Patent number: 11329047
    Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Yih Wang, Abhishek A. Sharma, Tahir Ghani, Allen B. Gardiner, Travis W. Lajoie, Pei-hua Wang, Chieh-jen Ku, Bernhard Sell, Juan G. Alzate-Vinasco, Blake C. Lin
  • Patent number: 11316068
    Abstract: An optoelectronic semiconductor chip and a method for producing an optoelectronic semiconductor chip are disclosed. In an embodiment, a chip includes a semiconductor body comprising a plurality of emission regions, first and second contact points, a rewiring structure and first and second connection points, wherein each emission region is contacted via the first and second contact points and configured to be operated separately from one another, wherein the rewiring structure electrically conductively connects each first contact point to an associated first connection point, wherein the rewiring structure electrically conductively connects every second contact point to an associated second connection point, wherein at least one of the connection points does not overlap with a contact point which is electrically conductively connected to this connection point in a vertical direction, and wherein each first connection point is disposed laterally directly adjacent to a further first connection point.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: April 26, 2022
    Assignee: OSRAM OLED GMBH
    Inventors: Dominik Scholz, Alexander F. Pfeuffer
  • Patent number: 11307200
    Abstract: The present disclosure provides an improved field effect transistor and device that can be used to sense and characterize a variety of materials. The field effect transistor and/or device including the transistor may be used for a variety of applications, including genome sequencing, protein sequencing, biomolecular sequencing, and detection of ions, molecules, chemicals, biomolecules, metal atoms, polymers, nanoparticles and the like.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: April 19, 2022
    Inventor: Bharath Takulapalli
  • Patent number: 11309192
    Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: April 19, 2022
    Assignee: Intel Corporation
    Inventors: Kristof Kuwawi Darmawikarta, Robert May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov
  • Patent number: 11295986
    Abstract: Vertical field-effect transistor (VFET) devices and methods of forming the VFET devices are provided. The methods may include forming a first channel region and a second channel region on a substrate, forming a recess in the substrate between the first and second channel regions by removing a portion of the liner and a portion of the substrate, forming a bottom source/drain region in the recess of the substrate, forming a capping layer on the bottom source/drain region, removing the liner and the capping layer, forming a spacer on the substrate and the bottom source/drain region, and forming a gate structure on side surfaces of the first and second channel regions.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: April 5, 2022
    Inventors: Min Gyu Kim, Sa Hwan Hong
  • Patent number: 11289329
    Abstract: Methods and apparatus for method for filling a feature with copper. In some embodiments, the methods include: (a) depositing a first cobalt layer via a physical vapor deposition (PVD) process atop a substrate field and atop a sidewall and a bottom surface of a feature disposed in a substrate to form a first cobalt portion atop the substrate field and a second cobalt portion atop the sidewall; (b) depositing copper atop the first cobalt portion atop the substrate field; and (c) flowing the copper disposed atop the first cobalt portion atop the substrate field over the second cobalt portion and into the feature, wherein the first cobalt portion atop the substrate field reduces the mobility of copper compared to the mobility of copper over the second cobalt portion.
    Type: Grant
    Filed: January 25, 2020
    Date of Patent: March 29, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Rui Li, Xiangjin Xie, Fuhong Zhang, Shirish Pethe, Adolph Allen, Lanlan Zhong, Xianmin Tang
  • Patent number: 11289611
    Abstract: A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: March 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Zhenyu Lu, Hongbin Zhu, Gordon A. Haller, Roger W. Lindsay, Andrew Bicksler, Brian J. Cleereman, Minsoo Lee
  • Patent number: 11289647
    Abstract: A memory cell includes: a first electrode; a resistive material layer comprising one horizontal portion and two vertical portions that are respectively coupled to ends of the horizontal portion; and a second electrode, wherein the second electrode is partially surrounded by a top boundary of the U-shaped profile and the first electrode extends along part of a bottom boundary of the U-shaped profile.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh Mo, Shih-Chi Kuo
  • Patent number: 11289365
    Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device including an air gap underneath passive devices. The semiconductor device generally includes a substrate layer, a passive device layer, and a dielectric layer disposed between the substrate layer and the passive device layer, wherein the dielectric layer includes an air gap disposed beneath at least one passive device in the passive device layer.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: March 29, 2022
    Assignee: Qualcomm Incorporated
    Inventors: Junjing Bao, Ye Lu, Haitao Cheng
  • Patent number: 11282845
    Abstract: A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jun Fang, Fei Wang, Saniya Rathod, Rutuparna Narulkar, Matthew Park, Matthew J. King
  • Patent number: 11282745
    Abstract: Methods and apparatus for filling a high aspect ratio feature such as a via with ruthenium including: contacting a ruthenium liner with a ruthenium precursor within a high aspect ratio feature such as a via, wherein the ruthenium liner has a top surface within a high aspect ratio feature such as a via, and wherein the top surface comprises a halogen material such as iodine or bromine. Embodiments also relate to selective deposition of ruthenium within a high-aspect ratio feature such as a via.
    Type: Grant
    Filed: April 28, 2019
    Date of Patent: March 22, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Sang-Ho Yu, Seshadri Ganguli
  • Patent number: 11276618
    Abstract: An apparatus is provided which comprises: a woven fiber layer, a first resin layer on a first surface of the woven fiber layer, a second resin layer on a second surface of the woven fiber layer, the second surface opposite the first surface, and the first and the second resin layers comprising cured resin, a third resin layer on the first resin layer, and a fourth resin layer on the second resin layer, the third and the fourth resin layers comprising an uncured resin, and wherein the fourth resin layer has a thickness greater than a thickness of the third resin layer. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Jonathan Rosch, Andrew J. Brown