Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A first insulating layer is directly on sidewalls of the lower fin portion of the fin, wherein the first insulating layer is a non-doped insulating layer comprising silicon and oxygen. A second insulating layer is directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin, the second insulating layer comprising silicon and nitrogen. A dielectric fill material is directly laterally adjacent to the second insulating layer directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin.

Abstract: Apparatuses and methods for arranging compensation capacitors are described. An example apparatus includes: a first conductive layer including a portion; a second conductive layer: a contact coupled to the portion of the first conductive layer; a third conductive layer between the first conductive layer and the second conductive layer, coupled to the contact; one or more capacitor elements wherein each capacitor element of the one or more capacitor elements includes one end coupled to the second conductive layer and another end coupled to the third conductive layer.

Abstract: Micro light-emitting diode (LED) displays, and fabrication and assembly of micro LED displays, are described. In an example, a pixel element for a micro-light emitting diode (LED) display panel includes a blue color nanowire or nanopyramid LED above a first nucleation layer above a substrate, the blue color nanowire or nanopyramid LED including a first GaN core. A green color nanowire or nanopyramid LED is above a second nucleation layer above the substrate, the green color nanowire or nanopyramid LED including a second GaN core. A red color nanowire or nanopyramid LED is above a third nucleation layer above the substrate, the red color nanowire or nanopyramid LED including a GaInP core.

Abstract: A semiconductor device includes a substrate, an isolation feature over the substrate, a first device fin protruding from the substrate and through the isolation feature, and a second device fin protruding from the substrate and through the isolation feature. The semiconductor device also includes a dielectric fin disposed between the first and second device fins and a metal gate stack engaging the first and second device fins. The dielectric fin separates the metal gate stack into first and second segments and provides electrical isolation between the first and second segments. A portion of the isolation feature is directly under a bottom surface of the dielectric fin.

Abstract: An integrated circuit semiconductor device includes a plurality of cylindrical structures separated from each other on a substrate; and a plurality of supporters having an opening region exposing side surfaces of the plurality of cylindrical structures, the plurality of supporters being in contact with the side surfaces of the plurality of cylindrical structures and supporting the plurality of cylindrical structures, wherein each of the plurality of supporters has both side surfaces having slopes and has a top width that is less than a bottom width.

Abstract: The present application discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a gate dielectric layer, a floating gate, a first dielectric layer and a control gate. The gate dielectric layer is disposed on the substrate. The floating gate is disposed on the gate dielectric layer and has at least one tip on a top surface of the floating gate. The first dielectric layer is disposed on the floating gate. The control gate is disposed above the first dielectric layer and at least partially overlaps the floating gate.

Abstract: A method of fabricating an electronic device can include forming a plurality of vertical channels having sidewalls over a substrate, and forming gate dielectric regions over portions of the vertical channels and planar regions adjoining the vertical channels. Gate electrode regions are then formed over portions of the gate dielectric regions. The gate electrode material and the vertical channel region are doped and sized to enable full depletion of charges during operation. Source and body tie regions are formed on the vertical sidewalls by doping with a p-type or n-type dopant. Dielectric regions over the gate electrode regions are formed to electrically isolate the gate electrode regions from the source regions. A metallic layer is formed over the first side of the substrate having the vertical channels. Stress is then induced within the substrate by annealing and/or cooling to separate a semiconductor region of the substrate and the metallic layer from the remaining portion of the substrate.

Abstract: The present disclosure provides a semiconductor device structure with a bottom capacitor electrode having a crown-shaped structure and an interconnect portion and a method for forming the same. The semiconductor device structure includes a capacitor contact disposed over a semiconductor substrate, and a dielectric layer disposed over the capacitor contact. The semiconductor device structure also includes a patterned mask disposed over the dielectric layer, and a bottom capacitor electrode disposed over and electrically connected to the capacitor contact. The bottom capacitor electrode includes a base layer disposed between the capacitor contact and the dielectric layer, and a surrounding portion disposed over the base layer and along sidewalls of the dielectric layer and the patterned mask. The bottom capacitor electrode also includes a first interconnect portion disposed in the dielectric layer and substantially parallel to the base layer.

Abstract: Micro light-emitting diode displays having nanophosphors, and methods of fabricating micro light-emitting diode displays having nanophosphors, are described. In an example, a pixel structure includes a substrate having a plurality of conductive interconnect structures in a first dielectric layer thereon. A plurality of micro light emitting diode devices is in a second dielectric layer above the first dielectric layer, including a first blue micro light emitting diode device, a second blue micro light emitting diode device, and a green micro light emitting diode device. A transparent conducting oxide layer is disposed on the plurality of micro light emitting diode devices and on the second dielectric layer. A phosphor layer is on the transparent conducting oxide layer at a location vertically aligned with the first blue micro light emitting diode device but not at a location vertically aligned with the second blue micro light emitting diode device.

Abstract: Pixel architectures for low power micro light-emitting diode displays are described. In an example, a micro light emitting diode pixel structure includes a substrate having a plurality of conductive interconnect structures in a first dielectric layer thereon. A plurality of micro light emitting diode devices is in a second dielectric layer above the first dielectric layer, individual ones of the plurality of micro light emitting diode devices electrically coupled to a corresponding one of the plurality of conductive interconnect structures. The plurality of micro light emitting diode devices includes an orange micro light emitting diode device, a green micro light emitting diode device, and a blue micro light emitting diode device. A transparent conducting oxide layer is disposed on the plurality of micro light emitting diode devices and on the second dielectric layer.

Abstract: A semiconductor device with redistribution layers formed utilizing dummy substrates is disclosed and may include forming a first redistribution layer on a first dummy substrate, forming a second redistribution layer on a second dummy substrate, electrically connecting a semiconductor die to the first redistribution layer, electrically connecting the first redistribution layer to the second redistribution layer, and removing the dummy substrates. The first redistribution layer may be electrically connected to the second redistribution layer utilizing a conductive pillar. An encapsulant material may be formed between the first and second redistribution layers. Side portions of one of the first and second redistribution layers may be covered with encapsulant. A surface of the semiconductor die may be in contact with the second redistribution layer. The dummy substrates may be in panel form. One of the dummy substrates may be in panel form and the other in unit form.

Abstract: Methods for DRAM device with a buried word line are described. The method includes forming a metal cap layer and a molybdenum conductor layer in a feature on a substrate. The method includes depositing the metal cap layer on the substrate by physical vapor deposition (PVD) and depositing the molybdenum conductor layer by atomic layer deposition (ALD) on the metal cap layer.

Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having an oxygen vacancy passivating bottom spacer. In a non-limiting embodiment of the invention, a first semiconductor fin is formed in a first region of a substrate and a second semiconductor fin is formed in a second region of the substrate. A bilayer bottom spacer is formed in direct contact with sidewalls of the semiconductor fins. The bilayer bottom spacer includes a first layer and an oxygen-donating second layer positioned on the first layer. A first dielectric film is formed on the sidewalls of the first semiconductor fin. The first dielectric film terminates on the first layer. A second dielectric film is formed on the sidewalls of the second semiconductor fin. The second dielectric film extends onto a surface of the oxygen-donating second layer.

Abstract: An integrated circuit includes a polysilicon resistor having a plurality of segments, including first, second and third segments, the second segment located between and running about parallel to the first and third segments. A first header connects the first and second segments, and a second header connects the second and third segments. A first metal silicide layer located over the first header extends over the first and second segments toward the second header. A second metal silicide layer located over the second header extends over the second and third segments toward the first header. A dielectric layer is located over and contacts the first, second and third segments between the first and second metal silicide layers.

Abstract: A method includes forming a pad layer and a mask layer over a substrate; patterning the mask layer, the pad layer, and the substrate to form pads, masks, and first and semiconductor fins over the substrate; forming a liner covering the pads, the masks, and the first and second semiconductor fins; removing a first portion of the liner to expose sidewalls of the first semiconductor fin, while leaving a second portion of the liner covering sidewalls of the second semiconductor fin; forming an isolation material over the substrate; and performing a CMP process to the isolation material until a first one of the pads over the second semiconductor fin is exposed; and etching back the isolation material and the second portion of the liner.

Abstract: A semiconductor device structure and a manufacturing method thereof are provided. The semiconductor device structure includes a semiconductor substrate having an active component region and a non-active component region, a first dielectric layer, a second dielectric layer, high resistivity metal segments, dummy stacked structures and a metal connection structure. The high resistivity metal segments are formed in the second dielectric layer and located in the non-active component region. The dummy stacked structures are located in the non-active component region, and at least one dummy stacked structure penetrates through the first dielectric layer and the second dielectric layer and is located between two adjacent high resistivity metal segments. The metal connection structure is disposed on the second dielectric layer, and the high resistivity metal segments are electrically connected to one another through the metal connection structure.

Abstract: Embodiments described herein provide for post deposition anneal of a substrate, having an amorphous carbon layer deposited thereon, to desirably reduce variations in local stresses thereacross. In one embodiment, a method of processing a substrate includes positioning a substrate, having an amorphous carbon layer deposited thereon, in a first processing volume, flowing an anneal gas into the first processing volume, heating the substrate to an anneal temperature of not more than about 450° C., and maintaining the substrate at the anneal temperature for about 30 seconds or more. Herein, the amorphous carbon layer was deposited on the substrate using a method which included positioning the substrate on a substrate support disposed in a second processing volume, flowing a processing gas into the second processing volume, applying pulsed DC power to a carbon target disposed in the second processing volume, forming a plasma of the processing gas, and depositing the amorphous carbon layer on the substrate.

Abstract: A method of manufacturing a 3D semiconductor device, the method including forming a first target structure, the first target structure including at least one upper gate, at least one bottom gate, and a dielectric separation layer disposed between and separating the at least one upper gate and the at least one bottom gate; removing material in a plurality of material removal areas in the first target structure, the plurality of material removal areas including at least one material removal area that extends through the at least one upper gate to a top of the dielectric separation layer; and forming a first contact establishing a first electrical connection to the upper gate and a second contact establishing a second electrical connection to the at least one bottom gate, such that the first contact and second contact are independent of each other.

Abstract: An integrated circuit structure includes: a semiconductor nanowire extending in a length direction and including a body portion; a gate dielectric surrounding the body portion; a gate electrode insulated from the body portion by the gate dielectric; a semiconductor source portion adjacent to a first side of the body portion; and a semiconductor drain portion adjacent to a second side of the body portion opposite the first side, the narrowest dimension of the second side of the body portion being smaller than the narrowest dimension of the first side. In an embodiment, the nanowire has a conical tapering. In an embodiment, the gate electrode extends along the body portion in the length direction to the source portion, but not to the drain portion. In an embodiment, the drain portion at the second side of the body portion has a lower dopant concentration than the source portion at the first side.

Abstract: A method forms a first voltage node of a high voltage component of a microelectronic device. The method also forms a plurality of dielectric layers. The method also forms a second voltage node of the high voltage component of the microelectronic device in a fourth position such that the plurality of dielectric layers is between the first voltage node and the second voltage node. During the forming a second voltage node step, a portion of a third layer in the plurality of dielectric layers, in a region outwardly positioned relative to the second voltage node, is removed to expose the second layer, in the plurality of dielectric layers, in the region.