Abstract: An apparatus and method for performing quality inspections on a test surface based on optically stimulated emission of electrons. In one embodiment, the apparatus comprises a device for producing optical radiation having a plurality of different spectrum lines, selecting at least one of the spectrum lines, and directing the selected spectrum line to the test surface, and circuitry for detecting a current of photoelectrons emitted from the test surface, generating a signal indicative of photoelectron current, and for indicating a condition of quality based on the generated signal indicative of the photoelectron current.

Abstract: A method for selective etching in the manufacture of a semiconductor device comprises: forming a layer (6) of silicon-germanium on a substrate (1) of monocrystalline silicon or on a substrate at least comprising a surface layer of monocrystalline silicon, depositing at least a dielectric layer (7) on the silicon-germanium layer (6) and patterning the resultant structure (8), whereafter the dielectric layer (7) and the silicon-germanium layer (6) are etched away within a predetermined region (9). Preferably, the silicon-germanium layer (6) is amorphous, whereby the dielectric layer (7) is deposited on the amorphous silicon-germanium layer (6) in such a manner to prevent crystallization of the amorphous layer. After etching the structure may be heat-treated such that the amorphous layer crystallizes. The method is preferably applicable for etching an emitter window in the manufacture of a bipolar transistor having a self-registered base-emitter structure.

Abstract: A multi-layer film 10 is formed by stacking a Si1-x1-y1Gex1Cy1 layer (0?x1<1 and 0<y1<1) having a small Ge mole fraction, e.g., a Si0.785Ge0.2C0.015 layer 13, and a Si1-x2-y2Gex2Cy2 layer (0<x2?1 and 0?y2<1) (where x1<x2 and y1>y2) having a high Ge mole fraction, e.g., a Si0.2Ge0.8 layer 12. In this manner, the range in which the multi-layer film serves as a SiGeC layer with C atoms incorporated into lattice sites extends to high degrees in which a Ge mole fraction is high.

Abstract: A method of forming a polycrystalline silicon layer. An amorphous silicon layer on a substrate is completely melted using a laser beam passed through a mask so as to form a polycrystalline silicon layer. The upper portion of the polycrystalline silicon layer is then re-melted and re-crystallized using a laser beam passed through a mask. The mask includes a high transmittance region for completely melting the amorphous silicon layer and a low transmittance region for re-melting the upper portion of the polycrystalline silicon layer.

Abstract: When carrying workpieces from a loading area in which the workpieces are handled into a heat treatment furnace to make the workpieces subjected to a heat treatment process using a predetermined process gas, the loading area is evacuated and controlled at a predetermined low negative pressure. An exhaust for evacuating the loading area is connected to the loading area, and a controller controls the exhaust so that the loading area is maintained at the predetermined low negative pressure. A specific gas and particles contained in a gas discharged from the loading area are removed by filters.

Abstract: A fabrication method for an electron source substrate comprises: a measurement step wherein at least one of a substrate, having a plurality of pairs of electrodes on the surface thereof, and measurement means for measuring the position of the substrate in at least one direction of the mutually orthogonal XYZ directions, is scanned relatively in one direction, thereby measuring the substrate position; a control step for controlling the discharge position of droplets containing electroconductive thin-film material onto the substrate from an ink-jet head, based on the measurement results; and a discharge step for discharging the droplets between the pairs of electrodes while relatively scanning at least one of the ink-jet head and substrate in one direction; wherein the scanning direction in the measurement step and the scanning direction in the discharge step are generally parallel; and wherein the measurement step and the discharge step are performed in a single scan.

Abstract: A semiconductor-manufacturing tool has two load locks, one for semiconductor wafers entering the tool for processing and the other for wafers leaving the tool after being processed. The load locks are of a new generation capable of being evacuated or vented in shorter times than load locks of the prior art, and permit high throughput. The tool is associated with three atmospheric wafer-handling robots to obtain the high throughput permitted by the load locks. One robot transfers wafers to be processed from a supply to a wafer pre-aligner, another robot transfers wafers from the wafer pre-aligner to the load lock for wafers entering the tool, and the third transfers processed wafers from the load lock for wafers leaving the tool back to the supply.

Abstract: A method of forming a ferroelectric film includes the steps of forming a layer by a material that takes a metal state in a reducing ambient and an oxide state in an oxidizing ambient, and depositing a ferroelectric film on a surface of the layer by supplying gaseous sources of the ferroelectric film and an oxidizing gas and causing a decomposition of the gaseous sources at the surface of said layer, wherein the step of depositing the ferroelectric film is started with a preparation step in which the state of the surface of said layer is controlled substantially to a critical point in which the layer changes from the metal state to the oxide state and from the oxide state to the metal state.

Abstract: Methods, systems, products and apparatuses are disclosed herein relating to registration and asymmetrically deposited films, and more specifically, to reducing asymmetrically deposited film induced registration measurement error.

Abstract: A method of assembling a semiconductor device package includes first attaching a semiconductor device to a die-pad area of a leadframe. Electrical connections are then between electrical contact areas on the semiconductor device and electrical connection areas on the leadframe to form a device/leadframe assembly. An adhesion enhancing coating is then deposited on the exposed surface of the device frame/leadframe assembly before encapsulating the coated device leadframe assembly in an electrically insulating material.

Abstract: A strained silicon MOSFET utilizes a strained silicon layer formed on a silicon geranium layer. Strained silicon and silicon germanium are removed at opposing sides of the gate and are replaced by silicon regions. Deep source and drain regions are implanted in the silicon regions, and the depth of the deep source and drain regions does not extend beyond the depth of the silicon regions. By forming the deep source and drain regions in the silicon regions, detrimental effects of the higher dielectric constant and lower band gap of silicon geranium are reduced.

Abstract: A memory device and method of manufacturing thereof, wherein a silicide material is selectively formed over active regions of a memory device. A silicide material may also be formed on the top surface of wordlines adjacent the active regions during the selective silicidation process. A single nitride insulating layer is used, and portions of the workpiece are covered with photoresist during the formation of the silicide material.

Abstract: A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a thyristor thereon. The thyristor has at least four layers, with three P-N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.

Abstract: A conductive structure for use in a semiconductor device includes a multilayer structure. A first layer includes a material containing silicon, e.g., polysilicon and silicon germanide. A barrier layer is formed over the first layer, with the barrier layer including metal silicide or metal silicide nitride. A top conductive layer is formed over the barrier layer. The top conductive layer can include metal or metal silicide. Selective oxidation can be performed to reduce the amount of oxidation of selected materials in a structure containing multiple layers, such as the multi-layer conductive structure. The selective oxidation is performed in a single-wafer rapid thermal processing system, in which a selected ambient, including hydrogen, is used to ensure low oxidation of a selected material, such as tungsten or a metal nitride.

Abstract: A method of forming a conductive structure having a length that is less than the length define by photolithographic patterning. A silicon layer (12) is formed in a MeOx dielectric layer (11) is photolithographically patterned to a predetermined first length. A metal layer (31) is formed conformally to at least the sidewalls of the silicon layer and then is reacted with the silicon to form a metal silicide (41). In particular, metal silicide abutments (411,412) are formed contiguous to sidewalls (421,422) of a reduced conductor (42). The remaining metal layer and the metal silicide are etched away, resulting in a conductor having predetermined second length that is less than the predetermined first length.

Abstract: A method of polishing the surface of a semiconductor wafer such that the adherence of abrasive particles to the surface of the wafer is minimized, resulting in a semiconductor wafer having a reduced number of pits. The invented method has two stages. The first stage follows traditional polishing practice using chemical mechanical polishing. The second stage diverges from traditional practices and provides for a final polishing step or steps involving the polishing of the wafer with a polishing solution having no abrasive particles.

Abstract: A method is provided for plasma ashing to remove photoresist remnants and etch residues that are formed during preceding plasma etching of dielectric layers. The ashing method uses a two-step plasma process involving an hydrogen-containing gas, where low or zero bias is applied to the substrate in the first cleaning step to remove significant amount of photoresist remnants and etch residues from the substrate, in addition to etching and removing detrimental fluoro-carbon residues from the chamber surfaces. An increased bias is applied to the substrate in the second cleaning step to remove the remains of the photoresist and etch residues from the substrate. The two-step process reduces the memory effect commonly observed in conventional one-step ashing processes. A method of endpoint detection can be used to monitor the ashing process.

Abstract: A method of press-working an inorganic substrate, which method uses a vacuum press machine having an air plunger type pressurization system and comprises bringing upper and lower heat plates which have been heated up to a predetermined temperature into contact with a combination set disposed between the upper and lower heat plates after or before the initiation of pressure reduction of a press atmosphere or under a reduced pressure and then carrying out a low pressure loading of from the initiation of pressurization to 0.05 Mpa over 10 seconds or longer and a press machine which is suitable for the above press-working method and which can set and control a low-pressure of 0.02 MPa or lower and comprises an air plunger that works as an air damper when the upper heat plate descends.

Abstract: A MOSFET device in strained silicon-on-SiGe and a method of forming the device are described. The said device achieves reduced junction leakage due to the lower band-gap values of SiGe. The method consists of forming isolation trenches in a composite strained-Si/SiGe substrate and growing a liner oxide by wet oxidation such that oxidation is selective to SiGe only, with negligible oxidation of silicon surfaces. Selective oxidation results in oxide encroachment under strained-Si, thereby reducing the junction area after device fabrication is completed. Reduced junction area leads to reduced n+/p or p+/n junction leakage current.

Abstract: An integrated enterprise resource planning and manufacturing system which includes a middleware component, a fabrication facility coupled to the middleware component, a real time dispatcher application program interface coupled between the fabrication facility and the middleware component, a work in progress application program interface coupled between the fabrication facility and the middleware component, and an enterprise resource planning system coupled to the middleware component. The fabrication facility includes a manufacturing execution system and a real time dispatch system. The manufacturing execution system tracks overall processing of semiconductor wafers. The real time dispatch system provides near real time information regarding processing of semiconductor wafers. The real time dispatcher application program interfaces publishing information to the middleware component.