Abstract: The present invention provides a method for inspecting a silicon wafer making it possible to identify and efficiently detect a new defect affecting a device fabricating process, a method for manufacturing a silicon wafer enabling manufacture of wafers not having the defect, a method for fabricating a semiconductor device using the silicon wafer not having this defect, and the silicon wafer not having the defect. When a silicon wafer is inspected, inspection is made for a defect having the entire defect size of 0.5 ?m or more in which microdefects gather in a colony state.

Abstract: An protective film and a resin layer are stacked on an insulation substrate on which a TFT is formed, and after a contact hole is formed in the resin layer, the protective film below the contact hole is etched and removed. A pixel display electrode is allowed to contact a drain electrode at the area of the contact hole; thus, a liquid crystal display is formed. A cut-out section, which communicates with the lower layer is formed in the drain electrode in the area of the contact hole. Upon forming a TFT section island-shape semiconductor layer so as to provide a TFT, a hole section island-shape semiconductor layer is also formed in the area of the contact hole. With this arrangement, it is possible to provide a manufacturing method of a liquid crystal display which can avoid the occurrence of a step discontinuity in the pixel display electrode and the subsequent disconnection in the pixel display electrode.

Abstract: A liquid crystal display device and a fabricating method thereof wherein an adhesive force between a seal and a lower plate is improved upon bonding of an upper plate to the lower plate. In high aperture liquid crystal display panels, organic protective films are used to reduce dielectric constants. However, the seal, used when bonding the upper and lower plates of the liquid crystal panel, generally do not adhere well to organic materials. In this invention, holes are generated in the organic protective film so that the seal bonds with inorganic materials such as the lower glass plate or the gate insulating film. A method is also presented to precisely control the amount of the gate insulating film to be etched using the EPD window technique.

Abstract: An integrated circuit transistor structure can include a gate electrode on a substrate and a source/drain region in the substrate adjacent to the gate electrode. An anti-punchthrough layer, separate from the substrate, is adjacent to the source/drain region.

Abstract: A polarizing plate produced according to the present invention includes a polarizing film and a protective layer bonded to a surface of the polarizing film, where the protective layer has no irregularities like record grooves caused by stretching of the polarizing film, so that the polarizing plate with an improved appearance provides clear images even when reflected light is applied. Such a polarizing plate is produced by laminating a protective layer on at least one surface of a polarizer while limiting moisture content of the polarizer to a range from 5% to 30%. A value for the moisture content is obtained by a calculation based on an equation of moisture content (%)=[(A?B)/B]×100, when A denotes weight of the polarizer before bonding and B denotes weight of the polarizer after being kept in a dryer of 120° C. for seven hours.

Abstract: A semiconductor package includes a relatively thin substrate epoxy attached to a packaging substrate, such as a lead frame. A relatively thick semiconductor epoxy is attached to a semiconductor. The relatively thin substrate epoxy and the relatively thick semiconductor epoxy are attached to one another forming a stack including the packaging substrate, the relatively thin substrate epoxy, the relatively thick semiconductor epoxy, and the semiconductor. A housing encloses the stack.

Abstract: A method of manufacturing a high performance MOS device and transistor gate stacks comprises forming a gate dielectric layer over a semiconductor substrate; forming a barrier layer over the gate dielectric layer by an ALD type process; and forming a gate electrode layer over the barrier layer. The method enables the use of hydrogen plasma, high energy hydrogen radicals and ions, other reactive radicals, reactive oxygen and oxygen containing precursors in the processing steps subsequent to the deposition of the gate dielectric layer of the device. The ALD process for forming the barrier layer is performed essentially in the absence of plasma and reactive hydrogen radials and ions. This invention makes it possible to use oxygen as a precursor in the deposition of the metal gates. The barrier film also allows the use of hydrogen plasma in the form of either direct or remote plasma in the deposition of the gate electrode.

Abstract: A manufacturing method for a semiconductor device is provided, wherein a silicon germanium (Si1-xGex; SiGe) layer and a strained silicon layer are sequentially formed on a semiconductor substrate. A gate oxide layer and a gate structure are further formed on the strained silicon layer. The gate structure and the strained silicon layer are heavily doped with n-type dopants to form a compressed gate and source/drain regions, respectively. A cap layer is further formed over the semiconductor substrate, followed by conducting an annealing process. The cap layer is subsequently removed.

Abstract: The present invention disclosed a method for manufacturing a semiconductor device on a semiconductor substrate, the method comprising the steps of: forming a gate dielectric layer on the semiconductor substrate. A gate is formed on the gate dielectric layer. A first ion implantation is performed to form extended source and drain shallow junctions in the semiconductor substrate. Spacer are formed on the side wall of the gate with liner between the gate and the spacers. The source and drain region is formed by performing a second ion implantation. A thermal annealing is used to eliminate the implantation defect and active the dopants. A surface treatment is used to form selective polycrystalline silicon on the gate and the source and drain region, thereby forming raised source and drain. A Cobalt layer is formed on the selective polycrystalline silicon.

Abstract: A system delivers radiation to a substrate with a radiation source to generate radiation having a source intensity distribution pattern; and a redistribution radiation guide adapted to receive the radiation from the radiation source and to direct the radiation from one region to different regions on the substrate so that the substrate intensity distribution pattern is different from the source pattern.

Abstract: A process for depositing a low dielectric constant layer (k<3) on a flat panel display and a flat panel display. The process includes reacting one or more organosilicon compounds with an oxygen containing compound at an RF power level from about 0.345 W/cm2 to about 1.265 W/cm2. The flat panel display includes a plasma display panel having a first substrate, a plurality of barriers deposited on the first substrate, a second substrate, a low dielectric constant layer (k<3) deposited on the second substrate, and a plurality of ground electrodes formed between the barriers and the dielectric layer.

Abstract: Systems and methods consistent with principles of the present invention allow contactless measuring of various kinds of electrical activity within an integrated circuit. The invention can be used for high-bandwidth, at speed testing of various devices on a wafer during the various stages of device processing, or on packaged parts at the end of the manufacturing cycle. Power is applied to the test circuit using conventional mechanical probes or other means, such as CW laser light applied to a photoreceiver provided on the test circuit. The electrical test signal is introduced into the test circuit by stimulating the circuit using a contactless method, such as by directing the output of one or more modelocked lasers onto high-speed receivers on the circuit, or by using a high-speed pulsed diode laser.

Abstract: A circuit feature that is interior to a packaged integrated circuit is modified by first identifying a trimming point on the interior circuit feature using an x-ray inspection system. Coordinates of the trimming point are then related to the coordinates of a visible reference marker. The relationship between the visible reference marker and the trimming point is then used to position a cutting tool over the trimming point. Finally, the cutting tool is used to make one or more cuts into the packaged integrated circuit, until the interior circuit feature has been acceptably modified at the trimming point.

Abstract: A method of fabricating a double gate MOSFET device is provided. The present invention overetches a silicon layer overlying a buried oxide layer using a hard mask of cap oxide on the silicon layer as an etching mask. As a result, source, drain and channel regions are formed extending from the buried oxide layer, and a pair of recesses are formed under the channel regions in the buried oxide layer. The channel is a fin structure with a top surface and two opposing parallelly sidewalls. The bottom recess is formed under each opposing sidewall of the fin structure. A conductive gate layer is formed straddling the fin structures. The topography of the conductive gate layer significantly deviates from the conventional plainer profile due to the bottom recess structures under the channel regions, and a more uniformly distributed doped conductive gate layer can be obtained.

Abstract: Stress balanced semiconductor device packages, a method of forming, and a method of modifying a mold segment for use in the method are disclosed. A semiconductor die is attached to one side of a substrate having discrete conductive elements such as a ball grid array (BGA) on the opposing side thereof. An envelope of encapsulant material is disposed over the semiconductor die on one side of the substrate while a stress balancing structure comprising at least one stem member and at least one transversely extending branch member formed of encapsulant material is disposed over the opposing side of the substrate in an arrangement which does not interfere with the discrete conductive elements. The envelope and the stress balancing structure may be simultaneously formed.

Abstract: A method of forming layers, in the same device material, with different thickness or layer height in a semiconductor device comprises forming device material layer or gate electrode layer disposable parts in selected regions of the device layer. The disposable parts can be formed by doping the selected regions to the desired depth d. The as-deposited thickness t of this device layer can be adjusted or modulated after the patterning of the individual devices by removing the disposable parts.

Abstract: Oxide particles with a doping component distributed in the core and a shell surrounding the core, which can be prepared by first introducing the doping into the core of a metal oxide or metalloid oxide via an aerosol in a pyrogenic process, subsequently coating the doped core with a salt solution of a metal or metalloid, drying it and optionally calcining it; which particles can be employed for chemical-mechanical polishing.

Abstract: In a method of manufacturing a semiconductor device, a semiconductor layer is patterned to form a source region, a channel region, and a drain region in the semiconductor layer. The channel region extends between the source region and the drain region. Corners of the channel region are rounded by annealing the channel region to form a nano-rod structure. Part of the nano-rod structure is then used as a gate channel. Preferably, a gate dielectric and a gate electrode both wrap around the nano-rod structure, with the gate dielectric being between the nano-rod structure and the gate electrode, to form a transistor device.

Abstract: The invention provides a liquid crystal light valve that makes it possible to increase the life of a polarizer at a light-exiting-surface side of the liquid crystal light valve by reducing the burden thereon, and a projection display device that incorporates the liquid crystal light valve. In liquid crystal light valves that modulate incident light in accordance with image information, at least two corresponding polarizers are provided respectively at the light-exiting-surface sides of liquid crystal panels.

Abstract: An integrated circuit package, and manufacturing method therefor, is provided. A substrate is provided having solder openings therein and a conductive layer thereon. The conductive layer is processed to form a plurality of pads over the solder openings in the substrate. A mask is formed over the plurality of pads and openings formed in the mask over at least two pads of the plurality of pads. An integrated circuit die is bonded over the substrate using a conductive adhesive where the conductive adhesive is placed in the openings in conductive contact with at least two pads of the plurality of pads.