Patents Examined by John F. Niebling
  • Patent number: 6861303
    Abstract: Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alternatively, threshold voltage (VT) implants can be introduced at one or more of the gate, source and drain regions to improve noise performance of the JFET. Additionally, fabrication of such a JFET can be facilitated forming the entire JFET structure concurrently with a CMOS fabrication process and/or with a BiCMOS fabrication process.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: March 1, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Pinghai Hao, Fan-Chi Hou, Imran Khan
  • Patent number: 6861676
    Abstract: The present invention provides a fabricating process for forming a flexible substrate, including the steps of: providing the substrate which is composed of a top plate and a bottom plate, and then a positive electrode layer and a organic electro-luminescence (EL) are formed in sequence on the bottom plate; after that, a same axial downward patterned template is pressed onto the bottom plate for “micro-patterning”, and thus the positive electrode layer and the organic electro-luminescence (EL) layer on the bottom plate are patterned in the same axial; providing a top plate, on which a metal layer as a negative electrode is formed; similarly, a same axial upper patterned template is pressed onto the top plate for “micro-patterning”, and thus the metal layer on the top plate is patterned in the same axial; finally, superimposing the top plate on the bottom plate so that the axis of patterned positive electrode layer and patterned organic EL layer crisscross with the axis of patterned metal layer to construct a c
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: March 1, 2005
    Assignee: Industrial Technology Research Institute
    Inventors: Cheng-Tang Pan, Hung-Yi Lin, Wu-Tung Chuan
  • Patent number: 6861274
    Abstract: An electroosmotic pump may be fabricated using semiconductor processing techniques with a nanoporous open cell dielectric frit. Such a frit may result in an electroosmotic pump with better pumping capabilities.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: March 1, 2005
    Assignee: Intel Corporation
    Inventors: R. Scott List, Alan Myers, Quat T. Vu
  • Patent number: 6859262
    Abstract: A system delivers radiation to a substrate with a radiation source to generate radiation having a source intensity distribution pattern; and a redistribution radiation guide adapted to receive the radiation from the radiation source and to direct the radiation from one region to different regions on the substrate so that the substrate intensity distribution pattern is different from the source pattern.
    Type: Grant
    Filed: December 6, 2000
    Date of Patent: February 22, 2005
    Assignee: Tegal Corporation
    Inventor: Tue Nguyen
  • Patent number: 6858487
    Abstract: The present invention disclosed a method for manufacturing a semiconductor device on a semiconductor substrate, the method comprising the steps of: forming a gate dielectric layer on the semiconductor substrate. A gate is formed on the gate dielectric layer. A first ion implantation is performed to form extended source and drain shallow junctions in the semiconductor substrate. Spacer are formed on the side wall of the gate with liner between the gate and the spacers. The source and drain region is formed by performing a second ion implantation. A thermal annealing is used to eliminate the implantation defect and active the dopants. A surface treatment is used to form selective polycrystalline silicon on the gate and the source and drain region, thereby forming raised source and drain. A Cobalt layer is formed on the selective polycrystalline silicon.
    Type: Grant
    Filed: January 2, 2003
    Date of Patent: February 22, 2005
    Assignee: United Microelectronics Corp.
    Inventors: Ming-Sheng Yang, Water Lur
  • Patent number: 6858505
    Abstract: An integrated circuit transistor structure can include a gate electrode on a substrate and a source/drain region in the substrate adjacent to the gate electrode. An anti-punchthrough layer, separate from the substrate, is adjacent to the source/drain region.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: February 22, 2005
    Assignee: Samsung Electronics Co. Ltd.
    Inventor: Byung-Jun Park
  • Patent number: 6858548
    Abstract: A process for depositing a low dielectric constant layer (k<3) on a flat panel display and a flat panel display. The process includes reacting one or more organosilicon compounds with an oxygen containing compound at an RF power level from about 0.345 W/cm2 to about 1.265 W/cm2. The flat panel display includes a plasma display panel having a first substrate, a plurality of barriers deposited on the first substrate, a second substrate, a low dielectric constant layer (k<3) deposited on the second substrate, and a plurality of ground electrodes formed between the barriers and the dielectric layer.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: February 22, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Tae Kyung Won, Quanyuan Shang, William R. Harshbarger
  • Patent number: 6858524
    Abstract: A method of manufacturing a high performance MOS device and transistor gate stacks comprises forming a gate dielectric layer over a semiconductor substrate; forming a barrier layer over the gate dielectric layer by an ALD type process; and forming a gate electrode layer over the barrier layer. The method enables the use of hydrogen plasma, high energy hydrogen radicals and ions, other reactive radicals, reactive oxygen and oxygen containing precursors in the processing steps subsequent to the deposition of the gate dielectric layer of the device. The ALD process for forming the barrier layer is performed essentially in the absence of plasma and reactive hydrogen radials and ions. This invention makes it possible to use oxygen as a precursor in the deposition of the metal gates. The barrier film also allows the use of hydrogen plasma in the form of either direct or remote plasma in the deposition of the gate electrode.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: February 22, 2005
    Assignee: ASM International, NV
    Inventors: Suvi Haukka, Hannu Huotari
  • Patent number: 6859241
    Abstract: A polarizing plate produced according to the present invention includes a polarizing film and a protective layer bonded to a surface of the polarizing film, where the protective layer has no irregularities like record grooves caused by stretching of the polarizing film, so that the polarizing plate with an improved appearance provides clear images even when reflected light is applied. Such a polarizing plate is produced by laminating a protective layer on at least one surface of a polarizer while limiting moisture content of the polarizer to a range from 5% to 30%. A value for the moisture content is obtained by a calculation based on an equation of moisture content (%)=[(A?B)/B]×100, when A denotes weight of the polarizer before bonding and B denotes weight of the polarizer after being kept in a dryer of 120° C. for seven hours.
    Type: Grant
    Filed: October 16, 2001
    Date of Patent: February 22, 2005
    Assignee: Nitto Denko Corporation
    Inventors: Eiji Hamamoto, Youichirou Sugino, Kazuki Tsuchimoto, Senri Kondou, Seiichi Kusumoto
  • Patent number: 6859031
    Abstract: Systems and methods consistent with principles of the present invention allow contactless measuring of various kinds of electrical activity within an integrated circuit. The invention can be used for high-bandwidth, at speed testing of various devices on a wafer during the various stages of device processing, or on packaged parts at the end of the manufacturing cycle. Power is applied to the test circuit using conventional mechanical probes or other means, such as CW laser light applied to a photoreceiver provided on the test circuit. The electrical test signal is introduced into the test circuit by stimulating the circuit using a contactless method, such as by directing the output of one or more modelocked lasers onto high-speed receivers on the circuit, or by using a high-speed pulsed diode laser.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: February 22, 2005
    Assignee: Credence Systems Corporation
    Inventors: Nader Pakdaman, Steven Kasapi, Itzik Goldberger
  • Patent number: 6858506
    Abstract: A manufacturing method for a semiconductor device is provided, wherein a silicon germanium (Si1-xGex; SiGe) layer and a strained silicon layer are sequentially formed on a semiconductor substrate. A gate oxide layer and a gate structure are further formed on the strained silicon layer. The gate structure and the strained silicon layer are heavily doped with n-type dopants to form a compressed gate and source/drain regions, respectively. A cap layer is further formed over the semiconductor substrate, followed by conducting an annealing process. The cap layer is subsequently removed.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: February 22, 2005
    Assignee: Macronix International Co., Ltd.
    Inventor: Kent Kuohua Chang
  • Patent number: 6858942
    Abstract: A semiconductor package includes a relatively thin substrate epoxy attached to a packaging substrate, such as a lead frame. A relatively thick semiconductor epoxy is attached to a semiconductor. The relatively thin substrate epoxy and the relatively thick semiconductor epoxy are attached to one another forming a stack including the packaging substrate, the relatively thin substrate epoxy, the relatively thick semiconductor epoxy, and the semiconductor. A housing encloses the stack.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: February 22, 2005
    Assignee: Altera Corporation
    Inventors: Eng-Chew Cheah, Sydney Larry Anderson
  • Patent number: 6856375
    Abstract: The invention provides a liquid crystal light valve that makes it possible to increase the life of a polarizer at a light-exiting-surface side of the liquid crystal light valve by reducing the burden thereon, and a projection display device that incorporates the liquid crystal light valve. In liquid crystal light valves that modulate incident light in accordance with image information, at least two corresponding polarizers are provided respectively at the light-exiting-surface sides of liquid crystal panels.
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: February 15, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Akitaka Yajima, Mutsuya Furuhata, Hisashi Iechika, Toshio Matsumiya
  • Patent number: 6855606
    Abstract: In a method of manufacturing a semiconductor device, a semiconductor layer is patterned to form a source region, a channel region, and a drain region in the semiconductor layer. The channel region extends between the source region and the drain region. Corners of the channel region are rounded by annealing the channel region to form a nano-rod structure. Part of the nano-rod structure is then used as a gate channel. Preferably, a gate dielectric and a gate electrode both wrap around the nano-rod structure, with the gate dielectric being between the nano-rod structure and the gate electrode, to form a transistor device.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: February 15, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yu Chen, Yee-Chia Yeo, Fu-Liang Yang, Chenming Hu
  • Patent number: 6855635
    Abstract: Oxide particles with a doping component distributed in the core and a shell surrounding the core, which can be prepared by first introducing the doping into the core of a metal oxide or metalloid oxide via an aerosol in a pyrogenic process, subsequently coating the doped core with a salt solution of a metal or metalloid, drying it and optionally calcining it; which particles can be employed for chemical-mechanical polishing.
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: February 15, 2005
    Assignee: Degussa AG
    Inventors: Kai Schumacher, Helmut Mangold
  • Patent number: 6856403
    Abstract: An apparatus and method for performing quality inspections on a test surface based on optically stimulated emission of electrons. In one embodiment, the apparatus comprises a device for producing optical radiation having a plurality of different spectrum lines, selecting at least one of the spectrum lines, and directing the selected spectrum line to the test surface, and circuitry for detecting a current of photoelectrons emitted from the test surface, generating a signal indicative of photoelectron current, and for indicating a condition of quality based on the generated signal indicative of the photoelectron current.
    Type: Grant
    Filed: September 11, 2003
    Date of Patent: February 15, 2005
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Christopher S. Welch, Daniel F. Perey
  • Patent number: 6854179
    Abstract: A circuit feature that is interior to a packaged integrated circuit is modified by first identifying a trimming point on the interior circuit feature using an x-ray inspection system. Coordinates of the trimming point are then related to the coordinates of a visible reference marker. The relationship between the visible reference marker and the trimming point is then used to position a cutting tool over the trimming point. Finally, the cutting tool is used to make one or more cuts into the packaged integrated circuit, until the interior circuit feature has been acceptably modified at the trimming point.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: February 15, 2005
    Assignee: Agilent Technologies, Inc.
    Inventors: Albert An-Bon Yeh, Regina Nora Pabilonia, Robert William Kressin, Wei Liu
  • Patent number: 6855574
    Abstract: Stress balanced semiconductor device packages, a method of forming, and a method of modifying a mold segment for use in the method are disclosed. A semiconductor die is attached to one side of a substrate having discrete conductive elements such as a ball grid array (BGA) on the opposing side thereof. An envelope of encapsulant material is disposed over the semiconductor die on one side of the substrate while a stress balancing structure comprising at least one stem member and at least one transversely extending branch member formed of encapsulant material is disposed over the opposing side of the substrate in an arrangement which does not interfere with the discrete conductive elements. The envelope and the stress balancing structure may be simultaneously formed.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: February 15, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Blaine J. Thurgood
  • Patent number: 6855573
    Abstract: An integrated circuit package, and manufacturing method therefor, is provided. A substrate is provided having solder openings therein and a conductive layer thereon. The conductive layer is processed to form a plurality of pads over the solder openings in the substrate. A mask is formed over the plurality of pads and openings formed in the mask over at least two pads of the plurality of pads. An integrated circuit die is bonded over the substrate using a conductive adhesive where the conductive adhesive is placed in the openings in conductive contact with at least two pads of the plurality of pads.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: February 15, 2005
    Assignee: St Assembly Test Services Ltd.
    Inventors: Jian Jun Li, Il Kwon Shim, Guruprasad Badakere
  • Patent number: 6855605
    Abstract: A method of forming layers, in the same device material, with different thickness or layer height in a semiconductor device comprises forming device material layer or gate electrode layer disposable parts in selected regions of the device layer. The disposable parts can be formed by doping the selected regions to the desired depth d. The as-deposited thickness t of this device layer can be adjusted or modulated after the patterning of the individual devices by removing the disposable parts.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: February 15, 2005
    Assignee: Interuniversitair Microelektronica Centrum (IMEC)
    Inventors: Malgorzata Jurczak, Rita Rooyackers, Emmanuel Augendre, Goncal Badenes