Abstract: The present disclosure provides a semiconductor die structure with air gaps for reducing capacitive coupling between conductive features and a method for preparing the semiconductor die structure. The semiconductor die structure includes a substrate; a first supporting backbone disposed on the substrate; a second supporting backbone disposed on the substrate; a first conductor block disposed on the first supporting backbone; a second conductor block disposed on the second supporting backbone; a third conductor block disposed above the substrate and connected to the first conductor block and the second conductor block; and an air gap structure disposed between the first conductor block, the second conductor block, and the third conductor block, wherein the air gap structure comprises an air gap and a liner layer enclosing the air gap.

Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.

Abstract: The present technology relates to Provided are a semiconductor device in which an air gap structure can be formed in any desired region regardless of the layout of metallic wiring lines, a method for manufacturing the semiconductor device, and an electronic apparatus. A first wiring layer and a second wiring layer including a metallic film are stacked via a diffusion preventing film that prevents diffusion of the metallic film. The diffusion preventing film is formed by burying a second film in a large number of holes formed in a first film. At least the first wiring layer includes the metallic film, an air gap, and a protective film formed with the second film on the inner peripheral surface of the air gap, and the opening width of the air gap is equal to the opening width of the holes formed in the first film or is greater than the opening width of the holes.

Abstract: An electronic device package includes a substrate, a first semiconductor die, a second semiconductor die and an encapsulant. The substrate includes a first surface, and a second surface opposite to the first surface. The substrate defines a cavity recessed from the first surface. The first semiconductor die is disposed in the cavity. The second semiconductor die is disposed over and electrically connected to the first semiconductor die. The encapsulant is disposed in the cavity of the substrate. The encapsulant encapsulates a first sidewall of the first semiconductor die, and exposes a second sidewall of the first semiconductor die.

Abstract: An integrated circuit (IC) chip that includes a semiconductor substrate including active devices on its front side, and at least part of a power delivery network (PDN) on its back side, is disclosed. In one aspect, the PDN includes a power supply terminal (Vdd) and a reference terminal (Vss) at the back of the IC. A plurality of TSV (Through Semiconductor Via) connections through the substrate bring the power to the front of the substrate. A field effect transistor is integrated at the back side of the substrate, and includes a source electrode, a drain electrode, and a gate electrode, which are contacted at the back side of the substrate. The IC further includes a gate control terminal for controlling the gate voltage. The transistor is coupled between the power supply terminal and one or more of the active devices of the IC.

Abstract: A semiconductor package including a first semiconductor device, a second semiconductor device, an insulating encapsulant, a redistribution structure and a supporting element is provided. The insulating encapsulant encapsulates the first semiconductor device and the second semiconductor device. The redistribution structure is over the first semiconductor device, the second semiconductor device and the insulating encapsulant. The redistribution structure is electrically connected to the first semiconductor device and the second semiconductor device. The supporting element is embedded in one of the insulating encapsulant and the redistribution structure.

Abstract: A substrate with an electronic component embedded therein includes a core substrate including an insulating body having a first surface and a second surface, opposite to the first surface, a first wiring layer embedded in the insulating body such that one surface thereof is exposed from the first surface, and a second wiring layer disposed on the insulating body to protrude on the second surface, the core substrate having a cavity penetrating a portion of the insulating body from the first surface toward the second surface and having a stopper layer as a bottom surface thereof; an electronic component disposed on the stopper layer in the cavity; a first insulating material covering at least a portion of each of the core substrate and the electronic component; and a third wiring layer disposed on the first insulating material.

Abstract: A chip package structure including first and second insulating layers, first and second circuit structures, a chip on the first circuit structure, an encapsulant, a conductive through via, and first and second heat dissipation layers is provided. The first circuit structure is disposed at the first surface of the first insulating layer. The bottom electrode of the chip is electrically connected to the first circuit structure. The second circuit structure is disposed on the chip and electrically connected to the top electrode of the chip. The encapsulant encapsulates the first and second circuit structures and the chip. The conductive through via is disposed in the encapsulant and connects the first and second circuit structures. The second insulating layer is disposed on the second circuit structure. The first heat dissipation layer is disposed on the first insulating layer. The second heat dissipation layer is disposed on the second insulating layer.

Abstract: A method for forming a semiconductor device includes forming a gate structure on a substrate, and a doped source/drain region on each side of the gate structure; forming a first interlayer dielectric layer, the top surface of the first interlayer dielectric layer leveled with the top surface of the gate structure; forming a contact hole in the first interlayer dielectric layer on each side of the gate structure; forming a cobalt layer in the contact hole, the top surface of the cobalt layer lower than the top surface of the first interlayer dielectric layer; forming a protective layer to cover the cobalt layer, the top layer of the protective layer lower than the top surface of the first interlayer dielectric layer; and forming a second interlayer dielectric layer, the top surface of the second interlayer dielectric layer leveled with the top surface of the first interlayer dielectric layer.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a resistor structure. A resistive layer overlies a substrate. The resistor structure overlies the substrate. The resistor structure includes a resistor segment of the resistive layer and conductive via structures overlying the resistor segment. A ring structure encloses the resistor structure. The ring structure extends continuously from a first point above the conductive structures to a second point below a bottom surface of the resistive layer.

Abstract: A multi-chip package power module according to the present disclosure, comprising: multiple chips, including a first chip and a second chip that are arranged adjacently; a first conductive member, at least partially arranged between the first chip and the second chip, and a second conductive member, at least partially arranged between the first chip and the second chip, where the first conductive member is electrically connected to a power pin of the first chip, the second conductive member is electrically connected to a power pin of the second chip, and the multiple chips, the first conductive member and the second conductive member are all embedded in an insulating package material. For the multi-chip package power module according to the present disclosure, the power output current of the chip can be directly led out from two opposite sides through the conductive member to obtain a symmetrical path.

Abstract: A method for manufacturing LED devices is provided. The method comprises forming an epitaxial layer on a starter substrate, the epitaxial layer having a first surface that interfaces with the starter substrate and a second surface opposite to the first surface; establishing an adhesive bond between the second surface of the epitaxial layer and a carrier substrate having a pre-determined light transmittance; etching away the starter substrate; etching away part of the epitaxial layer to form a plurality of light emitting diode (LED) dies on a third surface of the epitaxial layer opposite to the second surface; establishing one or more conductive bonds between selected one or more LED dies, from the plurality of LED dies, and a backplane; weakening the adhesive bond between the second surface of the epitaxial layer and the carrier substrate; and moving the carrier substrate away from the backplane.

Abstract: A method of tie bar removal is provided. The method includes forming a leadframe including a tie bar and a flag. The tie bar extends from a side rail of the leadframe and has a distal portion at an angle different from a plane of the flag. A semiconductor die is attached to the flag of the leadframe. A molding compound encapsulates the semiconductor die, a portion of the leadframe, and the distal portion of the tie bar. The tie bar is separated from the molding compound with an angled cavity remaining in the molding compound.

Abstract: A semiconductor device includes a base structure including a first interlayer dielectric (ILD) layer and a contact including a conductive liner disposed along a conductive core, a conductive plug disposed on the conductive liner between the conductive core and the first ILD layer to a height of the base structure, and a metallization level including a conductive line and a self-aligned via underneath the conductive line disposed on the contact and the conductive plug. The conductive plug protects underlying material and increases connectivity between the self-aligned via and the contact that was reduced due to misalignment.

Abstract: In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.

Abstract: An interconnect structure of an integrated circuit (IC) in which dielectric material defines upper and lower cavities and a via cavity communicative with the upper and lower cavities at upper and lower ends thereof. The interconnect structure includes first conductive material filling the upper and lower cavities to form upper and lower lines, respectively and second conductive material filling the via cavity from the upper end thereof to the lower end thereof to form a via electrically communicative with the upper and lower lines.

Abstract: In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.

Abstract: An integrated circuit device includes a conductive line formed on a substrate, an insulating spacer covering side walls of the conductive line and extending parallel with the conductive line, and a conductive plug that is spaced apart from the conductive line with the insulating spacer therebetween. The insulating spacer includes an insulating liner contacting the conductive line, an outer spacer contacting the conductive plug, and a barrier layer between the insulating liner and the outer spacer to prevent oxygen atoms from diffusing into the outer spacer.

Abstract: A method for manufacturing a semiconductor device includes forming an interconnect in a first dielectric layer, and forming a second dielectric layer on the first dielectric layer. In the method, an etch stop layer is formed on the second dielectric layer, and a third dielectric layer is formed on the etch stop layer. A trench and an opening are formed in the third and second dielectric layers, respectively. A barrier layer is deposited in the trench and in the opening, and on a top surface of the interconnect. The method also includes removing the barrier layer from the top surface of the interconnect and from a bottom surface of the trench, and depositing a conductive fill layer in the trench and in the opening, and on the interconnect. A bottom surface of the trench includes the etch stop layer.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of interconnects spaced apart from each other on a substrate. The plurality of interconnects each have an upper portion and a lower portion. In the method, a plurality of spacers are formed on sides of the upper portions of the plurality of interconnects. A space is formed between adjacent spacers of the plurality of spacers on adjacent interconnects of the plurality of interconnects. The method also includes forming a dielectric layer on the plurality of spacers and on the plurality of interconnects. The dielectric layer fills in the space between the adjacent spacers of the plurality of spacers, which blocks formation of the dielectric layer in an area below the space. The area below the space is between lower portions of the adjacent interconnects.