Abstract: A 3D semiconductor device, the device including: a first level including a plurality of first metal layers; a second level, where the second level overlays the first level, where the second level includes at least one single crystal silicon layer, where the second level includes a plurality of transistors, where each of the plurality of transistors includes a single crystal channel, where the second level includes a plurality of second metal layers, where the plurality of second metal layers include interconnections between the plurality of transistors, and where the second level is overlaid by a first isolation layer; and a connective path between the plurality of transistors and the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, and where the via has a diameter of less than 400 nm and greater than 5 nm.

Abstract: A laser crystallizing apparatus may include a laser light source, an optical system, and an optical module. The laser light source may generate a laser beam. The optical system may convert the laser beam into a line laser beam. The optical module may disperse energy of the line laser beam in a first direction for generating a dispersed line laser beam. The first direction may be perpendicular to a lengthwise direction of the optical module.

Abstract: A protective film forming agent for dicing of semiconductor wafers for forming a protective film on the surface of the semiconductor wafers and capable of forming a protective film of high absorbance index, and a production method of semiconductor chips using the protective film forming agent. In a protective film forming agent containing a water-soluble resin, light absorber and solvent, a compound having a specific structure is used as the light absorber. The content of the light absorber in the protective film forming agent is 0.1% by mass or more and 10% by mass or less.

Abstract: A substrate processing device is provided with: a spin base disposed below a substrate grasped by a plurality of chuck members, the spin base transmitting the drive force of a spin motor to the chuck members; and a nozzle for supplying a processing fluid for processing the substrate to the top surface and/or bottom surface of the substrate. An IH heating mechanism of the substrate processing device has: a heat-generating member disposed between the substrate and the spin base; a heating coil disposed below the spin base; and an IH circuit for supplying electric power to the heating coil, whereby an alternating magnetic field applied to the heat-generating member is generated, and the heat-generating member is caused to generate heat.

Abstract: An apparatus for processing a substrate includes a chamber having a processing space inside, a substrate support unit that supports the substrate in the processing space, and a temperature adjustment unit that is installed in the chamber and that adjusts temperature in the processing space. The temperature adjustment unit includes a heating member that heats the processing space and a cooling member that cools the processing space. The cooling member is located closer to a central axis of the chamber than the heating member.

Abstract: A vapor deposition mask includes a metal mask and a resin mask having an opening. An inner wall surface for composing the opening has an inflection point in a thicknesswise cross section of the resin mask. When an intersection of a first surface, not facing the metal mask, of the resin mask and the inner wall surface is set to be a first intersection, an intersection of a second surface, facing the metal mask, of the resin mask and the inner wall surface is set to be a second intersection, and there is set a first inflection point first positioned from the first intersection toward the second intersection, an angle formed by a line connecting the first intersection and the first inflection point and the first surface is larger than an angle formed by a line connecting the first inflection point and the second intersection and the second surface.

Abstract: The present disclosure provides a one-time programmable capacitive fuse bit, including an upper plate, the upper plate includes a plurality of fuses arranged side by side and spaced by an internal from each other, middle portions of two adjacent fuses are connected to each other; a connecting portion connected to the fuse is disposed above two ends and the middle portion of each of the plurality of fuses; the fuse bit further includes a lower plate corresponding to the two ends and the middle portion of the fuse, the lower plate is disposed below the fuse; the lower plate corresponding to the middle portion of the fuse is opposite to the connecting portion corresponding to the middle portion of the fuse; a hollow portion is disposed between the lower plate corresponding to the middle portion of the fuse and the lower plate corresponding to both ends of the fuse.

Abstract: A single crystal substrate is provided and is characterized in that the single crystal substrate has a foundation substrate provided with a plurality of first grooves, which include a first crystal face and a second crystal face opposed to the first crystal face in an inner face thereof, and the extending direction of which is a<110> direction, and a plurality of second grooves, the extending direction of which intersects with the first grooves, and in which the first grooves are formed in a displaced manner in a depth direction, and a transverse cross-sectional shape of the second groove is a shape in which straight lines are open at an opening angle less than 180°. Further, it is preferred that an angle formed by the first crystal face and the second crystal face is more than 70.6°.

Abstract: In a described example, an electrical apparatus includes: a metal layer formed over a non-device side of a semiconductor device die, the semiconductor device die having devices formed on a device side of the semiconductor device die opposite the non-device side; a first side of the metal layer bonded to a die mount pad on a package substrate; a second side of the metal layer formed over a roughened surface on the non-device side of the semiconductor device die, the roughened surface having an average surface roughness (Ra) between 40 nm and 500 nm; bond pads on the semiconductor device die electrically coupled to conductive leads on the package substrate; and mold compound covering at least a portion of the semiconductor device die and at least a portion of the conductive leads.

Abstract: Disclosed is a substrate treating apparatus that performs a heat treatment to a substrate. The apparatus includes the following elements: a heat treating plate that heats the substrate; lift pins that deliver the substrate, a lift pin drive mechanism that causes the lift pins to move upwardly/downwardly; a casing that produces a heat treatment atmosphere; and a cooling base plate that suppresses transmission of heat from the heat treating plate. The lift pin drive mechanism is disposed below the cooling base plate.

Abstract: A semiconductor device having metamorphic high electron mobility transistor (HEMT)-heterojunction bipolar transistor (HBT) integration on a semiconductor substrate. An example semiconductor device generally includes a semiconductor substrate, a bipolar junction transistor (BJT) disposed above the semiconductor substrate and comprising indium, and a HEMT disposed above the semiconductor substrate and comprising indium.

Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side or a front side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form modified layers in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of cooling the polyester sheet in each of the plurality of separate regions corresponding to each device chip, pushing up each device chip through the polyester sheet, then picking up each device chip from the polyester sheet.

Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side or a front side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form shield tunnels in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of cooling the polyester sheet, pushing up each device chip through the polyester sheet, and picking up each device chip from the polyester sheet.

Abstract: Methods and apparatus for forming doped material layers in semiconductor devices using an integrated selective monolayer doping (SMLD) process. A concentration of dopant is deposited on a material layer using the SMLD process and the concentration of dopant is then annealed to diffuse the concentration of dopant into the material layer. The SMLD process conforms the concentration of dopant to a surface of the material layer and may be performed in a single CVD chamber. The SMLD process may also be repeated to further alter the diffusion parameters of the dopant into the material layer. The SMLD process is compatible with p-type dopant species and n-type dopant species.

Abstract: A laser processing apparatus includes an unloading/loading mechanism for unloading a wafer from and loading a wafer into a cassette placed on a cassette placing stand, a chuck table for rotatably holding the wafer unloaded from the cassette by the unloading/loading mechanism, an image capturing unit for capturing an image of a wafer, and a control unit. The control unit controls the unloading/loading mechanism to orient a mark indicating the crystal orientation of a processed wafer in a predetermined direction different from a direction in which the mark of an unprocessed wafer in the cassette is oriented, when the unloading/loading mechanism houses the processed wafer into the cassette.

Abstract: The inventive concept relates to a substrate treating apparatus and method for removing various types of treating liquid or cleaning solution films on an edge region of a substrate without damage to a treated surface even though the substrate is rotated in an eccentric state.

Abstract: A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side or a front side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form modified layers in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of cooling the polyolefin sheet in each of the plurality of separate regions corresponding to each device chip, pushing up each device chip through the polyolefin sheet, then picking up each device chip from the polyolefin sheet.

Abstract: The disclosure provides a display panel including a substrate layer, a thin film transistor (TFT) layer, and a gate on array (GOA) drive circuit. The TFT layer is disposed on the substrate layer, and a bending region is disposed on at least one side of the substrate layer near the TFT layer. The GOA drive circuit is disposed on the substrate layer, and the bending region is disposed between at least one side of the TFT layer and the GOA drive circuit. The auxiliary circuit is disposed on the substrate layer and is disposed correspondingly to the bending region.

Abstract: A calculating section of a control unit calculates a vertical position Defocus for a condensing lens using a height value H1 of a modified layer in a wafer that is set by a setting section according to the equation (1) below. Defocus=(thickness T1 of wafer?height value H1?b)/a??(1) The calculating section calculates an appropriate vertical position for the condensing lens according to the equation (1) depending on the height value H1 of the modified layer that is set by the setting section. Therefore, the vertical position of the condensing lens in laser processing operation can be determined more easily, and a time-consuming and tedious experiment for fine adjustment of the vertical position of the condensing lens does not need to be conducted.

Abstract: Provided is a semiconductor structure including a pad disposed over and electrically connected to an interconnect structure, wherein the pad has a probe mark, and the probe mark has a concave surface; a protective layer conformally covering the pad and the probe mark; and a bonding structure disposed over the protective layer, wherein the bonding structure includes: a bonding dielectric layer includes a first bonding dielectric material and a second bonding dielectric material on the first bonding dielectric material; a first bonding metal layer including a via plug and a metal feature, wherein the via plug penetrates through the first bonding dielectric material and the protective layer to electrically connect to the pad having the probe mark, the metal feature is located on the via plug and the first bonding dielectric material, and the metal feature is laterally surrounded by the second bonding dielectric material.