Patents Examined by John P. Trimmings
  • Logic analyzer systems and methods for programmable logic devices
    Patent number: 7536615
    Abstract: A programmable logic device includes, in accordance with one embodiment, a plurality of logic blocks; an interconnect structure adapted to route signals among the logic blocks; and a memory for storing data within the programmable logic device. A first set of the logic blocks are configured as logic analyzer trigger units adapted to each receive one or more input signals from within the programmable logic device and provide a corresponding trigger unit output signal. A portion of the memory stores a logic analyzer trigger expression, with the trigger unit output signals provided to the memory as address signals for the trigger expression.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: May 19, 2009
    Assignee: Lattice Semiconductor Corporation
    Inventors: David Pierce, Michael Hammer, Brian M. Caslis
  • Integrated circuit with scan-based debugging and debugging method thereof
    Patent number: 7533315
    Abstract: An integrated circuit comprises a test interface, an embedded in-circuit emulator, a circuit-under-debugging, and a memory. The embedded in-circuit emulator is used for software debugging via the test interface. The circuit-under-debugging comprises a scan chain dumping states of every delayed flip-flop (DFF) out of the circuit-under-debugging. The memory stores the states from the scan chain and transfers the states to a computer via the test interface.
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: May 12, 2009
    Assignee: Mediatek Inc.
    Inventors: I-Chieh Han, You-Ming Chiu
  • Method and apparatus for identifying outlier data
    Patent number: 7533313
    Abstract: A method for converting data includes generating a first data vector of data measurements related to processing of at least one workpiece. Each element of the first data vector is associated with at least one of a plurality of positions on the workpiece. A cumulative distribution of the elements in the first data vector is generated. An outlier region of the data measurements is identified based on the cumulative distribution. A binary outlier data vector is generated from the first data vector by assigning a first binary value to the data elements in the first data vector in the outlier region and assigning a second binary value to the remaining data elements in the first data vector.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: May 12, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael Alan Retersdorf, Michael G. McIntyre
  • Semiconductor memory test device and method thereof
    Patent number: 7533310
    Abstract: A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: May 12, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je-Young Park, Ki-Sang Kang
  • Programmable management IO pads for an integrated circuit
    Patent number: 7533311
    Abstract: A multi-port SERDES transceiver includes multiple parallel and serial ports, and the flexibility to connect any one of the parallel or serial ports to another parallel or serial port. The ports include programmable pads that are capable of supporting multiple different data protocols, timing protocols, electrical specifications, and input-output functions. A management data IO pad also enables the transceiver to support different electrical requirements and data protocols at the same time. The substrate layout of the transceiver is configured so that the parallel ports and the serial ports are on the outer perimeter. A logic core is at the center, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: May 12, 2009
    Assignee: Broadcom Corporation
    Inventors: Hoang T. Tran, Howard A. Baumer
  • Initial decision-point circuit operation mode
    Patent number: 7526693
    Abstract: A circuit that includes a controller and at least one control I/O pin. When the controller is placed into an initial state, the controller initializes the circuit into an initial operation mode. Depending on whether or not signal(s) satisfying predetermined criteria are applied to at least one of the control I/O pins, the controller will cause the circuit to enter one of two or more post-initial operation modes. Accordingly, by initializing the controller, and by controlling a signal on the control I/O pin(s), the operating mode of the circuit may be controlled. In one embodiment, a given control pin might be configurable to be both analog and digital, depending on the circuit's operation mode.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: April 28, 2009
    Assignee: Semiconductor Components Industries, LLC
    Inventors: David J. Willis, Matthew Austin Tyler, Justin Mark Gedge, Mark R. Whitaker
  • System and method to reduce LBIST manufacturing test time of integrated circuits
    Patent number: 7519889
    Abstract: A method to reduce logic built in self test manufacturing test time of integrated circuits, comprising: loading a plurality of test seeds in bulk into a locally accessible on-chip memory array locally disposed on an integrated circuit, each of the plurality of test seeds is associated with a set of LBIST control information; sending the plurality of test seeds from the locally accessible on-chip memory array repetitively into a pseudo-random pattern generator one at a time during an LBIST operation being under the control from the set of LBIST control information; generating random bit streams serially into a plurality of parallel shift registers of the integrated circuit through the use of the plurality of test seeds; and performing a logic built-in self test on a plurality of logic blocks in the integrated circuit to detect defects within the integrated circuit.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: April 14, 2009
    Assignee: International Business Machines Corporation
    Inventors: Daniel W. Cervantes, Joshua P. Hernandez, Tung N. Pham, Timothy M. Skergan
  • Method of configuring a system and system therefor
    Patent number: 7519883
    Abstract: A first scan data is received at a first scan chain and a representation of the first scan data is subsequently provided from the first scan chain to a second scan chain to test the second scan chain in response to a first value at a first bond pad. The first scan chain is bypassed to receive the first scan data at the second scan chain in response to a second value at the first bond pad.
    Type: Grant
    Filed: April 5, 2005
    Date of Patent: April 14, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Daniel E. Daugherty, Brett A. Tischler, Steven J. Kommrusch
  • Input/output circuit for handling unconnected I/O pads
    Patent number: 7519890
    Abstract: A method based on a circuit coupled to an input-output bond pad (I/O pad) in an integrated circuit including an input buffer, an output buffer and a pad management circuit. The pad management circuit receives a first data signal, a first output enable signal, and a configuration signal indicative of the connection state of the I/O pad, and generates a second data signal and a second output enable signal. When the configuration signal indicates the I/O pad is to be connected to a package pin, the pad management circuit couples the first data signal as the second data signal and couples the first output enable signal as the second output enable signal. When the configuration signal indicates the I/O pad is to be left unconnected, the pad management circuit asserts the second output enable signal and generates the second data signal having a predetermined value.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: April 14, 2009
    Assignee: Micrel, Inc.
    Inventor: Peter Chambers
  • Apparatus and method for integrated functional built-in self test for an ASIC
    Patent number: 7519886
    Abstract: We describe, in exemplary embodiments, an on-chip Functional Built-In Self Test (“FBIST”) mechanism for testing integrated circuits with internal memory state and complex transaction based interfaces. Such interfaces include system-on-chip applications, memory chip applications, and input/output (“IO”) protocol adapter chips.
    Type: Grant
    Filed: January 5, 2006
    Date of Patent: April 14, 2009
    Assignee: International Business Machines Corporation
    Inventors: Michael M. Tsao, R. Brett Tremaine
  • Obtaining test data for a device
    Patent number: 7519878
    Abstract: Obtaining test data for a device under test includes obtaining a first part of the test data by testing the device at first points of a range of parameters using progressive sampling, and obtaining a second part of the test data by testing the device at second points of the range of parameters using adaptive sampling.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: April 14, 2009
    Assignee: Teradyne, Inc.
    Inventor: Mark Rosen
  • Test pattern generator, test circuit tester, test pattern generating method, test circuit testing method, and computer product
    Patent number: 7516376
    Abstract: A test circuit tester includes a scan-chain input-output information generator that generates information for an input and an output of the scan chain that is scan-chain input-output information, based on input information for the scan chain; a test-circuit input-output information generator that generates information for an input and an output of the test circuit that is test-circuit input-output information, based on the scan-chain input-output information; an output unit that outputs the test-circuit input-output information generated; and a verifying unit that verifies the test circuit based on an output pattern output from the test circuit through the scan chains in response to input of the information for the input of the test circuit output to the test circuit, and the information for the output from the test circuit.
    Type: Grant
    Filed: October 20, 2004
    Date of Patent: April 7, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Osamu Okano, Hideaki Konishi
  • Testing circuit and related method of injecting a time jitter
    Patent number: 7516374
    Abstract: A testing method includes selecting a low-pass filter by simulation, generating testing signals with the low-pass filter receiving output signals of an under-test circuit, and outputting the testing signals to an input of the under-test circuit for predetermined measurements. A testing circuit and testing method achieve the same jitter injection as conventional high-speed testing instruments, but save testing cost.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: April 7, 2009
    Assignee: VIA Technologies Inc.
    Inventors: Jimmy Hsu, Min-Sheng Lin
  • Method and apparatus for analyzing delay in circuit, and computer product
    Patent number: 7516383
    Abstract: An extracting unit extracts unprocessed capturing destination in a circuit. A tracing unit traces an output branch point from a capturing destination and a determining unit determines an estimated failure site and a non-failure site in the circuit. A detecting unit narrows down an estimated failure site using a fail address. It is determined whether an identifying unit has identified a failure site. If the failure site has not been identified, a delay failure simulation is performed and a comparing unit compares the comparison result of the tester measurement and the result in the delay failure simulation to determine consistency between the results. The identifying unit identifies the failure site based on the consistency.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: April 7, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Mitsuhiro Hirano
  • Method for estimating and reporting the life expectancy of flash-disk memory
    Patent number: 7512847
    Abstract: A method for managing a memory device, a memory device so managed and a system that includes such a memory device. A value of a longevity parameter of the device is monitored after a data operation on the device in which the monitoring is performed by the device. A grade of the device is derived from the value. Preferred longevity parameters include a ratio of successfully-processed data to unsuccessfully-processed data and a deviation in a power consumption of the device. The grade serves as a forecast of a life expectancy of the memory. Preferred grades include: a comparison grade, a maximum grade, and an average grade.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: March 31, 2009
    Assignee: Sandisk IL Ltd.
    Inventors: Eyal Bychkov, Avraham Meir, Alon Ziegler, Itzhak Pomerantz
  • Checkpointing user design states in a configurable IC
    Patent number: 7512850
    Abstract: Some embodiments provide a configurable integrated circuit (IC) that has several configurable circuits and several user design state (UDS) circuits. The UDS circuits store user-design state values. The configurable IC also includes a debug network communicatively coupled to the UDS circuits. The debug network is for retrieving the user-design state values of several UDS circuits at various stoppages of the operation of the IC without retrieving configuration data that is used to configure the configurable circuits of the IC. The retrieved user-design state values at each stoppage are used as the checkpointed state of the IC while debugging the IC. In some embodiments, the debug network allows the checkpointing of only certain portions of the configurable IC.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: March 31, 2009
    Assignee: Tabula, Inc.
    Inventors: Jason Redgrave, Brad Hutchings, Herman Schmit, Steven Teig, Tom Kronmiller
  • Method and apparatus of defect areas management
    Patent number: 7512846
    Abstract: A method and the apparatus of defect areas management includes the steps as following: reading a defect area table in a random access memory; if the area is readable, then read the area. If the area is not accessible, then label and add one count in the defect area table of inability to read of the defect area, and else if the count of inability to read of the defect area is more than a predetermined value, then the defect area is defined as the area of being not to be read again. Then the defect area of being not to be read again is skipped and not to be read the next time in order to decrease the total access time.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: March 31, 2009
    Assignee: Quanta Storage Inc.
    Inventors: Shang-Hao Chen, Shiu-Ming Chu
  • Method and system for testing memory modules
    Patent number: 7509545
    Abstract: A method and system for testing memory modules is disclosed. The system includes a memory module and a connector configured to receive the module. The memory module is configured to operate in two modes: In the first operation mode the module uses a frequency between a low frequency and a high frequency. In the second operation mode, the module uses a frequency lower than the lower frequency. A control circuit is coupled to the connector. The control circuit is configured to apply a control signal to the circuit module when the circuit module is received in the connector. When the circuit module is received in the connector, the control signal is applied. This applied control signal causes the module to operate in the second operation mode.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: March 24, 2009
    Assignee: Smart Modular Technologies, Inc.
    Inventors: Mike H. Amidi, Michael Rubino, Larry C. Alchesky
  • System for phase tracking and equalization across a byte group for asymmetric control of high-speed bidirectional signaling
    Patent number: 7506222
    Abstract: A system for phase tracking and equalization across a byte group for asymmetric control of high-speed bidirectional signaling includes a slave device and a master device that is coupled to the slave device via a plurality of bidirectional data paths. The master device may adaptively modify transmit characteristics based upon data eye information sent via one or more unidirectional data paths by the slave device. The data eye information may correspond to an edge position of data signal transitions received by the slave device on each data path of the plurality of bidirectional data paths. In addition, the master device may modify data path equalization coefficients within the master device for a grouping of the bidirectional data paths such as a byte group, for example, dependent upon the data eye information.
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: March 17, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Gerald R. Talbot
  • Fast cyclic redundancy check (CRC) generation
    Patent number: RE40684
    Abstract: A CRC generation unit includes a number of CRC calculation assemblies to be selectively employed to incrementally calculate a CRC value for a first sequence of N data bytes. The calculation is iteratively performed, one iteration at a time. Further, the selection of the CRC calculation assemblies is made in accordance with the group size of each of a number of data word groups of the N data bytes. In one embodiment, the CRC calculation assemblies include a first assembly for incrementally calculate the CRC value for an iteration, whenever the group size is n/2 bytes or less for the iteration, and a second assembly for incrementally calculate the CRC value for an iteration, whenever the group size is more than n/2 bytes for the iteration. In one embodiment, the CRC generation unit is a shared resource to multiple network traffic flow processing units of a network traffic routing IC.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: March 24, 2009
    Inventor: Richard B. Keller