Abstract: A signature circuit in a semiconductor chip includes a signature program circuit configured to be programmed with signature information and to output a signature signal in response to the signature information; a signature output circuit configured to block the signature signal output by the signature program circuit during operation in a normal mode, and configured to pass the signature signal during operation in a test mode; and a pad-driving transistor directly coupled to the pad, configured to drive the pad during operation in the normal mode in response to an operation command, and configured to drive the pad during operation in the test mode in response to the signature signal output by the signature output circuit. The signature circuit outputs the signature information through a transistor for adjusting impedance to reduce a chip size by omitting an additional logic circuit for the signature circuit.

Abstract: A memory device includes an ECC and test circuit. In a normal mode, the circuit performs ECC conventional functions. In a test mode, the least significant bit of received data is used to generate test data. If the received bit is “0,” the test data bits are all “0,” and if the received bit is “1,” the test data bits are all “1.” The test data bits are applied to the ECC encoder that is used in normal operation. The ECC encoder is designed so that it generates ECC bits that have the same logic level as the test data bits. The test data bits and ECC bits are then written to a memory array and subsequently read. During the test mode, a logic circuit determines if the read data and check bits are all either “0” or “1” and outputs a corresponding test result bit from the memory device.

Abstract: In one embodiment, a method includes, providing a test program designed to control a circuit test system. The circuit test system has a plurality of test channels, each test channel of which is configured to be selectively coupled to a plurality of sub-channels under control of the test program. The method further includes 1) analyzing the test program to determine what combinations of channels, sub-channels and timing sets are required by the test program, and 2) in response to this analysis, creating a map of which timing sets, for which combinations of channels and sub-channels, should be pre-loaded into pin electronics that correspond to the test channels.

Abstract: A software implementation of a Reed-Solomon decoder placing a constant load on the processor of a computer. A Berlekamp-Massey Algorithm is used to calculate the coefficients of the error locator polynomial, a Chien Search is used to determine the roots of the error locator polynomial, and a Forney Algorithm is used to determine the magnitude of the errors in the received digital code word. Each step is divided into m small tasks where m is the number of computational blocks it takes to read in a code word and the processor can pipeline or parallel process one task from each step each time a block is read.

Abstract: A method for testing an integrated circuit device with asynchronous clocks or dissimilar design methodologies is provided. With the method, each clock domain has its own scan paths that do not cross domain boundaries. By eliminating the scanning across the boundaries, the requirement to have two clock grids in the asynchronously clocked domains may be eliminated. As a result, circuit area and design time with regard to the clock distribution design are reduced. In addition, removing the second clock grid, i.e. the high speed core or system clock, in the asynchronously clocked domains removes the requirement to have a multiplexing scheme for selection of clocking signals in the asynchronous domain. In addition to the above, the method provides boundary built-in-self-test logic for testing the functional crossing logic of boundaries between the clock domains in a functional mode of operation.

Abstract: A test system and methods using the test system correlate measurements of a device under test (DUT) regardless of which test fixture is used for in-fixture testing of the DUT. The test system includes test equipment, a test fixture that interfaces the DUT to the test equipment, a computer and a computer program executed by the computer. The computer program includes instructions that implement determining a port-specific difference array for test fixtures used with the test system. The difference array describes a difference between the test fixtures at a corresponding test port thereof. The method includes determining the difference array, measuring a performance of the DUT in a second test fixture, and applying the difference array such that the measured performance approximates a hypothetical DUT performance for the DUT as if mounted in a first test fixture.

Abstract: An integrated circuit with a multiplexer system and a control circuit is described. The multiplexer system has an output terminal connected to an output pin of the integrated circuit and input terminals connected to internal nodes of the integrated circuit. In a normal mode the control circuit generates the control signals so that any one of the internal nodes is connected to the output pin so that the integrated circuit can function flexibly. In a test mode so that a different internal node is connected to the output pin in each cycle of a test clock signal.

Abstract: Method, apparatus, and computer readable medium for generating test vectors for an integrated circuit (IC) under test is described. In one example, a test function is specified using at least one elementary function that encapsulates program code associated with an architecture of the IC under test. An engine is configured with device description data for the IC under test. The engine is executed with the test function as parametric input to generate the test vectors. In one example, the IC under test comprises a programmable logic device (PLD) and the test vectors include configuration data for configuring a pattern in the PLD and at least one test vector for exercising the pattern. The test vectors may be applied directly to the device or through automatic test equipment (ATE). Alternatively, the test vectors may be applied to a IC design simulation of the device.

Abstract: This invention provides a semiconductor memory device and its data writing method capable of saving the needed time to a minimum even in repeating a data write operation maximum number of times. More specifically, this invention provides a semiconductor memory device and its data writing method as follows. A flash memory 101 is set at a test mode by fixing the test pad TP at L level. When a verify operation passes, a verify pass signal input terminal (VPASS) of a data write controlling circuit WCC and a verify pass signal input terminal (VPASS) of a data write counter circuit WCT are fixed at L level by a verify pass signal invalidating means 3 although a verify circuit VC outputs an L level verify pass signal VPASS. A latch circuit LC holds a latched verify pass signal VPL at H level and a verify start signal input terminal (VR) of the verify circuit VC is fixed at L level. A write operation without a verify operation is repeated number of times preset in the data write counter circuit WCT.

Abstract: A system is provided that retrieves test information from a target integrated circuit. A serializer receives the test information in a first format and divides and reformats the test information into first and second serial messages. The serializer is located on the target integrated circuit and has a first serial output that sends the first serial message and a second serial output that sends the second serial message. A deserializer communicates with the first and second serial outputs and receives the first and second serial messages. The deserializer retrieves a first portion of the test information from the first serial message, a second portion of the test information from the second serial message, and reconstructs the test information from the first portion and the second portion.

Abstract: An integrated scannable interface for testing memory. The interface includes a selection device for selecting a signal from at least two input signals responsive to an activation signal, a first storage device coupled to the output of the selection device for storing the signal responsive to a first enable signal and generating an output signal for the memory. The first storage device is connected at the input node of the memory, and a second storage device is coupled at its input to the first storage device for storing the output signal responsive to a second enable signal and generating a test signal for testing the memory. The output signal is observed for debugging faults between the integrated scannable interface and the memory and for debugging faults between the first and second storage devices.

Abstract: An interface that communicates with first and second interface modules, an analyzer and an integrated circuit comprises a first path from the first and second interface modules and the analyzer to the integrated circuit. The first path includes a first serializer that serializes at least one of first control data and/or test data from at least one of the first and/or second interface modules. A second path from the integrated circuit to the first and second interface modules and the analyzer includes a high speed deserializer that deserializes serial data containing at least one of test result data and/or second control data from the integrated circuit. A frame sync module synchronizes data from the high speed deserializer to identify frames. The high speed deserializer outputs the second control data to at least one of the first and/or second interface modules. The frame sync module outputs the frames to the analyzer.

Abstract: An integrated circuit 2 including functional circuits 4, 6 and a diagnostic circuit 10 passes a functional signal and a diagnostic signal to/from the integrated circuit using a shared integrated circuit pin 14. The functional signal and the diagnostic signal have relative forms such that they can be simultaneously communicated and respective independent physical communication channels provided therefore. Examples are the diagnostic signal being used to frequency, phase, amplitude or otherwise modulate a functional signal being passed. A diagnostic interface circuit 18 is provided to recover the diagnostic signal from the combined functional and diagnostic signal or to combine the functional and diagnostic signals.

Abstract: An apparatus and associated methodology are provided to generate system test libraries for solution testing involving heterogeneous devices from different vendors. A unified user interface employs received information to execute the tests based on provided device and network topology libraries, generating the system library to perform the required end-to-end system testing. The unified user interface and the library generation mechanism provide a layer of abstraction avoiding complexities of the system configuration commands native to disparate devices.

Abstract: State spaces are traversed to produce test cases, or test coverage. Test coverage is a test suite of sequences. Accepting states are defined. Expected costs are assigned to the test graph states. Strategies are created providing transitions to states with lower expected costs. Linear programs and other approximations are discussed for providing expected costs. Strategies are more likely to provide access to an accepting state, based on expected costs. Strategies are used to append transitions to test segments such that the new test segment ends in an accepting state.

Abstract: Methods, apparatus, and systems for testing integrated circuits using one or more boundary scan cells are disclosed. The methods, apparatus, and systems can be used, for example, to apply at-speed test patterns through one or more boundary scan cells. For instance, in one exemplary nonlimiting embodiment, a circuit is disclosed comprising one or more boundary scan cells coupled to primary input ports or primary output ports of a circuit-under-test. The circuit further includes a boundary scan cell controller configured to apply test control signals to the one or more boundary scan cells. In this embodiment, the controller is configured to operate in a mode of operation whereby the controller applies test control signals to the one or more boundary scan cells that correspond to test control signals used to control one or more internal scan chains of the circuit-under-test during testing.

Abstract: A built-in self test unit reads tag bits of a predetermined cache entry and outputs these tag bits via an external interface. The built-in self test unit enters an emulation mode upon receipt of an emulation signal via the external interface when a first configuration register has a predetermined state. The built-in self test unit then reads tag bits upon each memory mapped read of a second configuration register. The read operation advances to next sequential tag bits upon each memory mapped read of the second configuration register. The tag bits include at least one valid bit and at least one dirty bit. The tag bits also include the most significant bits of the cached address.

Abstract: Systems and methods for performing logic built-in self-tests (LBISTs) in digital circuits, where boundary scan chains in functional blocks of the circuits can be selectively coupled/decoupled to isolate the functional blocks during LBIST testing. In one embodiment, processor cores of a multiprocessor chip are isolated and LBIST testing is performed to determine whether any of the processor cores is malfunctioning. If none of the processor cores malfunctions, the processor cores are tested in conjunction with the supporting functional blocks of the device to determine whether the multiprocessor is fully functional. If one or more processor cores malfunctions, these processor cores are isolated and the remaining processor cores are tested in conjunction with the supporting functional blocks of the device to determine whether the multiprocessor operates properly with reduced functionality.

Abstract: A semiconductor integrated circuit for intentionally and flexibly changing a monitoring subject bit if debugging is performed during software processing when a status change occurs. A replacement data register and a comparison address register, which are settable from a microprocessor, determine matching of an address input from the microprocessor and a comparison address value. When the addresses match in a test mode, instead of outputting normal status data, a predetermined value of the replacement data register is output in response to a read request from the microprocessor.

Abstract: A semiconductor device includes a circuit block; a first signal path for guiding a test signal to a signal input terminal of the circuit block; a second signal path for guiding a test clock to a clock input terminal of the circuit block; a third signal path for guiding a test output signal from a output terminal of the circuit block to a pad via a dummy latch; and a fourth signal path for guiding the test output signal from the output terminal of the circuit block, to another pad. A dummy latch latches the test output signal at substantially a same speed as an operational latch during a normal operation. The third signal path has a wiring delay time from the output terminal to the dummy latch that is substantially equal to a wiring delay time from the output terminal to the operational latch.