Patents Examined by John W. Cabeca
  • Patent number: 6922815
    Abstract: The invention is a computer-implemented method and apparatus for organizing Web pages and other computer files relative to each other in a manner analogous to a three or four dimensional spatial relationship and displaying multiple Web pages simultaneously in multiple panels of a computer monitor in accordance with said spatial organization, whereby despite the organization, at least one of the Web pages or files can be made to stay in the same panel of the display while the user navigates through the virtual multidimensional space.
    Type: Grant
    Filed: May 8, 2001
    Date of Patent: July 26, 2005
    Inventor: Mike Rosen
  • Patent number: 6891552
    Abstract: A system and method of displaying data representing an object of a class where the class has one or more attributes and each object has an attribute value associated with each attribute. The invention includes a collection class such that each statistic to be monitored is represented as an object of the class. The invention allows a software application to access the objects in a database. The invention provides a user interface (UI) attribute within the class that allows the user to specify the UI to display the attribute values of each accessed object. Each available UI is customized to a statistic to be monitored. Each available UI has a unique user interface attribute value. The invention supports any number of UIs supplied by the user, an application developer, or a third party.
    Type: Grant
    Filed: May 8, 2001
    Date of Patent: May 10, 2005
    Assignee: Microsoft Corporation
    Inventor: Eric N. Bush
  • Patent number: 6727924
    Abstract: A method of human-computer interfacing provides efficient intuitive controls in a three-dimensional space. The method provides a three-dimensional space, characterized by a z dimension approximately parallel to the user's direction of view, and x and y dimensions approximately orthogonal thereto. A control has x and y coordinate sets, and a z coordinate set that spans a range of values. The range can be infinite, making the control accessible at all depths, or can be a finite range, making the control accessible from that range of depths. Movement of a cursor into the control's region initiates user interaction according to the control. The control depth reduces the precision of depth perception required to find the control. Once the user is in the control region, the effective depth for interaction can be relative to the depth when the user entered, providing control interaction independent of entering depth.
    Type: Grant
    Filed: October 17, 2000
    Date of Patent: April 27, 2004
    Assignee: Novint Technologies, Inc.
    Inventor: Thomas G. Anderson
  • Patent number: 6621508
    Abstract: The menu displays of a base-station device and its data-correlated, portable device are managed. In the base-station device, first icon information corresponding to the menu is displayed on a first display screen. In the portable device, second icon information (corresponding to the first) is displayed on a second display screen. The base-station device has a first storage unit for storing the first icon information, a first display control unit for controlling a first display unit, and a first communication unit for communicating with the portable device. The portable device has a second storage unit for storing the second icon information, a second display control unit for controlling a second display unit, and a second communication unit for communicating with the base-station device and for matching pieces of display data stored in the first and second storage units. Thus, the size of the second icon information is maintained smaller than the size of the first.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: September 16, 2003
    Assignee: Seiko Epson Corporation
    Inventors: Atsushi Shiraishi, Keisuke Tsuji, Roy Nakashima
  • Patent number: 6614458
    Abstract: Computer instructions that operate to view a display of geometric constraints associated with a selected piece of geometry of a mechanical design and to drag and manipulate multiple geometric constraints of multiple pieces of geometry associated with the selected piece of geometry, when executed, is disclosed. In one embodiment, the computer instructions are part of a mechanical design software application. In one embodiment, the mechanical software application including the computer instructions are embodied in a distribution storage medium.
    Type: Grant
    Filed: January 31, 2000
    Date of Patent: September 2, 2003
    Assignee: Autodesk, Inc.
    Inventors: Mark Lambert, Paul Hanau
  • Patent number: 6583798
    Abstract: An on-object user interface (OOUI) for presenting information and controls to a user in response to an automatic action performed by an application program. The OOUI is associated with object that was subject to the automatic action. The OOUI comprises a first graphical indicator, a second graphical indicator and a context menu. The first graphical indicator is displayed in proximity to the object, in order to indicate that the automatic action was performed. The automatic action may comprise an auto-correct or an auto-format action. The automatic action may also comprise the setting of a property relating to formatting or positioning of the object in response to a user-initiated action. When user interaction with the first graphical indicator is detected, the first graphical indicator is changed to the second graphical indicator, which indicates that a context menu is available.
    Type: Grant
    Filed: July 21, 2000
    Date of Patent: June 24, 2003
    Assignee: Microsoft Corporation
    Inventors: Tjeerd Hoek, Glenn Frankel
  • Patent number: 6553467
    Abstract: An apparatus for accelerating the speed of memory access cycles in a multi-bank memory. The apparatus includes decode logic that pre-decodes bank information from a requested address signal while the corresponding request is queued in the request queue. The pre-decode logic is propagated to the memory controller, preferably by re-insertion into the request queue, to facilitate more rapid memory accesses.
    Type: Grant
    Filed: August 12, 1997
    Date of Patent: April 22, 2003
    Assignee: Intel Corporation
    Inventor: James M. Ottinger
  • Patent number: 6314492
    Abstract: System and method for controlling the contents of a browser cache. A data stream from a host server to a client browser includes a clear cache tag. Responsive to the clear cache tag, the browser clears its cache. The data stream may also include a start cache tag, and one or more data files which are cached by the client browser. Responsive to the clear cache tag, the browser cache is cleared of data files received in the data stream between the start cache tag and the clear cache tag, or alternatively of all data files in cache associated with a cache identifier received in the start cache and clear cache tags. Either the client local file system or a field in a cache table is used to differentiate between successive start cache tags.
    Type: Grant
    Filed: May 27, 1998
    Date of Patent: November 6, 2001
    Assignee: International Business Machines Corporation
    Inventors: Michael John Allen, Jonathan Penn Furminger
  • Patent number: 6293712
    Abstract: A computer-implemented method of constructing a stack unwind data structure is described. In one embodiment, the method commences when a procedure, which comprises part of the computer program, is compiled. The stack unwind data structure construction commences with determining whether the called procedure complies with a default condition for a predetermined characteristic. For example, it may be determined whether a stack frame for the procedure is of a fixed or variable size, with a fixed size stack frame comprising a default condition. If the procedure does not comply with, or varies from, the default condition for this predetermined characteristic, then an unwind record for the procedure is generated, and included within an entry associated with the procedure in the stack unwind data structure. Alternatively, should the procedure comply with the default condition, this unwind record is not generated and accordingly not included within the stack unwind data structure.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: September 25, 2001
    Assignee: Institute for the Development of Emerging Architectures, LLC
    Inventor: Cary A. Coutant
  • Patent number: 6272600
    Abstract: Memory transactions are carried out in an order that maximizes concurrency in a memory system such as a multi-bank interleaved memory system. Read data is collected in a buffer memory to be presented back to the bus in the same order as read transactions were requested. An adaptive algorithm groups writes to minimize overhead associated with transitioning from reading to writing into memory.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: August 7, 2001
    Assignee: Hyundai Electronics America
    Inventors: Gerry R. Talbot, Austen J. Hypher
  • Patent number: 6243797
    Abstract: A multiplexing arrangement for transferring data retrieved from a memory array to data outputs of a semiconductor memory, including a multiplexing circuit that is responsive to latency select signals to cause data retrieved sequentially from the memory array to be loaded into and read from data latch circuits of a data output register in a sequence that establishes a known delay between the time that data is retrieved from the memory array and stored in the data output register and the time that the data is read from the data output register. The delay allows data to be held in the data output register when the data is available and to be passed to the data outputs of the memory when desired.
    Type: Grant
    Filed: February 18, 1997
    Date of Patent: June 5, 2001
    Assignee: Micron Technlogy, Inc.
    Inventor: Todd A. Merritt
  • Patent number: 6240493
    Abstract: Method and apparatus for performing access censorship in a data processing system (10). In one embodiment, a digital data processing system (10) has a sub-system (34) that can be protected against intrusions, yet is still accessible and/or alterable under certain defined conditions. In a non-volatile storage portion (48) of the data processing system (10), censorship information is stored to enable an access control mechanism. Access control information (42) to selectively disable the access control mechanism is programmably generated. Additional access control information (44) can be employed to reprogram a data processing system (10) containing access protected data in a secure mode.
    Type: Grant
    Filed: April 17, 1998
    Date of Patent: May 29, 2001
    Assignee: Motorola, Inc.
    Inventors: Wallace B. Hardwood, III, James B. Eifert, Thomas R. Toms
  • Patent number: 6229737
    Abstract: A method and apparatus interleaves flash memory programming with E2ROM memory programming. In exemplary embodiments, the E2ROM accepts data in units of pages, whereas the flash memory accepts data in units of pages or individual bytes. As such, a first exemplary technique interleaves page-write E2ROM programming with page-write flash memory programming. A second exemplary technique interleaves page-write E2ROM programming with byte-write flash memory programming. Portions of the E2ROM programming are performed in parallel with portions of the flash memory programming, thereby expediting overall programming time (compared to performing E2ROM and flash memory programming in serial fashion).
    Type: Grant
    Filed: December 12, 1996
    Date of Patent: May 8, 2001
    Assignee: Ericsson Inc.
    Inventor: Joel James Walukas
  • Patent number: 6230245
    Abstract: A command generator for a dynamic random access memory decrements a counter from an initial counter value which is a function of the clock speed. The output of the counter is decoded to generate various command signals for the DRAM. In particular, each command signal is generated by a respective counter value, with the correspondency between counter values and command signals being a function of the clock speed. The counter decrements from larger initial values at higher clock speeds, and the command signals are generally issued by the decoder at higher counter values for higher clock speeds. As a result of the lack of correspondency between the timing of the command signals and the number of clock cycles occurring during a memory access, the timing of the command signals may be selected to optimize the speed of the DRAM desired despite substantial variations in clock speed.
    Type: Grant
    Filed: February 11, 1997
    Date of Patent: May 8, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • Patent number: 6219770
    Abstract: A method and apparatus operating within an object-oriented virtual memory management system. In the virtual memory management system, each page is referenced by traversing a series of mapping tables. Each mapping table is associated with one of a plurality of Partitioned Memory Objects (PMOs). Each PMO includes a plurality of MORs (Memory Object References). PMOs and NSKMPage data structures are collectively referred to as memory objects. When a memory object is duplicated (also called a “copy on write” or a “virtual copy”), the actual copy of the duplicated memory object is deferred until a write to the memory object actually occurs. MORs have a VCState field, which can have values of VCOriginal, VCDuplicate, VCSubdupFull, or VCSubdupPart. During a copy on write operation, a VCState of a MOR referring to the duplicated memory object is set to “VCDuplicate” and set to point to the memory object that was copied.
    Type: Grant
    Filed: March 23, 1998
    Date of Patent: April 17, 2001
    Assignee: Compaq Computer Corporation
    Inventor: Charles Robert Landau
  • Patent number: 6216211
    Abstract: A system and method for managing mirrored logical volumes are provided wherein a user designates one mirror of a given logical volume, having a first entry point, as the backup mirror, with a different entry point, for that logical volume; and thereafter, upon user issuance of an I/O command, appropriately valid mirror(s) are selected to be read from or written to as a function of which of the two entry points to the same data is specified.
    Type: Grant
    Filed: June 13, 1997
    Date of Patent: April 10, 2001
    Assignee: International Business Machines Corporation
    Inventors: Gerald Francis McBrearty, Johnny Meng-Han Shieh
  • Patent number: 6215737
    Abstract: Methods and apparatus for recording and playing back multi-channel digital audio having different sampling rates for different channels are provided. Recording is accomplished by sampling a plurality of channels of audio data and arranging the samples of the plurality of channels of audio data in most nearly the order needed during playback. Playback is accomplished by accessing the samples of the plurality of channels of audio data and converting the samples from digital to analog form. The playback may include deriving audio signals in a different format from the format in which the programming is recorded.
    Type: Grant
    Filed: April 24, 1998
    Date of Patent: April 10, 2001
    Assignee: WEA Manufacturing, Inc.
    Inventors: Gregory Thagard, Alan McPherson, Charles M. J. Mecca, Edwin Outwater, III, George Lydecker
  • Patent number: 6212616
    Abstract: The index field of an address maps to low order cache directory address lines. The remaining cache directory address line, the highest order line, is indexed by the parity of the address tag for the cache entry to be stored to or retrieved from the corresponding cache directory entry. Thus, even parity address tags are stored in cache directory locations with zero in the most significant index/address bit, while odd parity address tags are stored in cache directory locations with one in the most significant index/address bit. The opposite arrangement (msb 1=even parity; msb 0=odd parity) may also be employed, as may configurations in which parity supplies the least significant bit rather than the most significant bit. In any of these cases, even/odd parity is implied based on the location of the address tag within the cache directory.
    Type: Grant
    Filed: March 23, 1998
    Date of Patent: April 3, 2001
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, John Steven Dodson, Jerry Don Lewis
  • Patent number: 6212601
    Abstract: In one embodiment, there is a single integrated circuit microprocessor (10). The microprocessor has an instruction pipeline (12) which comprises an execution stage (12a) operable to process an information unit of a first length. The microprocessor further includes a cache circuit (20) comprising a memory (34) operable to store a transfer unit of information of a second length and accessible by the instruction pipeline. The second length corresponding to the capability of the cache circuit is greater than the first length corresponding to the execution stage operability. Lastly, the microprocessor includes a block move circuit (24) coupled to the cache circuit and operable to read/write a transfer unit of information of the first length into the memory of the cache circuit.
    Type: Grant
    Filed: August 29, 1997
    Date of Patent: April 3, 2001
    Assignee: Texas Instruments Incorporated
    Inventor: Jonathan H. Shiell
  • Patent number: 6209070
    Abstract: Disclosed is a system for transferring data involving a data movement, such as the duplication of address information, that includes two data movement components. A first data transfer from at least one source storage location to at least one target storage location is processed. A data structure indicates the source storage locations from which data was transferred during processing of the first data transfer. A second data transfer from a plurality of source storage locations to a plurality of target storage locations is processed. The data structure is then processed to determine the source storage locations included in the second data transfer that were not involved in the first data transfer. Data is then transferred from the source storage locations that were not involved in the first data transfer to the target storage locations that did not receive data during the processing of the first data transfer.
    Type: Grant
    Filed: March 20, 1998
    Date of Patent: March 27, 2001
    Assignee: International Business Machines Corporation
    Inventors: David Charles Reed, John Glenn Thompson