Abstract: A converter system that allows a host system using a first interface to use a second storage using a second interface. The invention provides a method to allow an ECKD MVS DASD storage using an ESCON interface to be used by an open system using a SCSI-type interface without changes to the ESCON storage or the open storage interfaces. The method also permits the SCSI-type interfaced open system to be physically located greater than 25 meters from the ESCON storage system. The method involves mapping the SCSI-type interface data and commands into parameters used and understood by the ESCON storage. The invention may also be implemented to provide a digital data storage medium containing the method of the invention and a digital apparatus capable of executing the invention.

Abstract: A multiprocessor processing 200 includes a memory system having a memory controller 202 for linking a plurality of processors 201 with an integrated memory 203. Integrated memory 203 comprises a plurality of static random access arrays 603 and a dynamic random access 407.

Abstract: A data backup and restore method and system for a multiple computer system environment is provided. The method/system comprises an automated approach for backing up and if necessary restoring computer system data from a first computer system to an auxiliary storage pool of a second computer system. At the first computer system, a renaming of system data to be backed up is accomplished such that the renamed system data designates the first computer system as the source system of the system data and comprises a name different from any name of system data at the second computer system. The renamed system data is then backup stored by the first computer system to the auxiliary storage pool of the second computer system. Multiple computer systems in the multisystem environment can be backed up to the same target computer system, either to the same auxiliary storage pool or to different auxiliary storage pools. Partial or complete restore of the backed up system data is also discussed.

Abstract: A method for efficiently updating as shared data structure in a multiprocessor environment comprises accessing a queue variable associated with time-based data events in the data structure. Information associated with the queue variable is used to determine the point of insertion of a new time-based data event. If a new time based data event is inserted, the data of the queue variable of a preceding time-based data event is altered to identify the new time-based data event. An embodiment employing a contention-free locking mechanism is also disclosed.

Abstract: A method and apparatus for utilizing a data cache in a system with both 2D and 3D graphics applications. In a specific embodiment of the present invention, a mode signal is received by the video system indicating whether a 2D or 3D application is to be used. Depending on the mode signal, either as a unified cache capable of being accessed by two separate data access streams, or two independent caches, each accessed by one data access stream.

Abstract: A method for exchanging information within a mesh network that has an array of nodes defined by four quadrants. The method includes the initial step of exchanging information from a set of nodes in one quadrant to a set of nodes located in an adjacent quadrant. The exchange of information simultaneously occurs in both a vertical and horizontal direction within the array. Information is then exchanged between nodes within the same quadrant and subquadrants.

Abstract: An actuator is provided with a step so as to allow FPC mounting surfaces of a read/write FPC band and of a relay FPC to be level with each other. Pointer information P4 in a ROM table is used to refer to a RAM table to acquire offset correction data. On-track control is effected at a cross point of two-phase servo signals N and Q. A value of this cross point is measured to find a position sensitivity correction value. A gap corresponding to encode loss is provided at the trailing position of each of sectors. In read operation, a sector pulse is generated with a delay corresponding to decode loss.

Abstract: A data transmission device which can read information on an IC card without changing a structure of a conventional floppy disc drive is provided. The IC card includes memory elements for storing information therein. The IC card is accommodated in the data transmission device and the data transmission device is attached to the floppy disc drive so that data stored in the IC card is read via the floppy disc drive. The IC card is electrically connected to the data transmission device. A magnetic head core unit of the data transmission device is magnetically connected to a magnetic head of the floppy disc drive so as to transmit data to the floppy disc drive via the magnetic head. A waveform of data read from the IC card is changed to a waveform which is conformable to a reproduction characteristic of the floppy disc drive.

Abstract: The present invention retrieves data across independent computer nodes of a server cluster by providing for I/O shipping of block level requests to peer intelligent host-bus adapters (hereinafter referred to as HBA). This peer-to-peer distribution of block I/O requests is transparent to the host. The HBA has the intelligence to decide whether to satisfy a block I/O request locally or remotely. Each HBA driver utilizes the I2O protocol, which allows peer-to-peer communication independent of the operating system or hardware of the underlying network. In a first embodiment of the present invention, local and remote storage channels, within a node, are supported by a single HBA. In a second embodiment of the present invention, local storage channels, within a node, are supported by one HBA, and the remote storage channel, within a node, is supported by a separate HBA.

Abstract: In a memory system having a plurality of banks which forms interleave groups for independently forming an interleave, when a memory error is detected in an operating system resident space, the group having the error is interchanged with another group that has not had any error yet. After a group interchange, a page having the error is also deallocated. When a determination is made that the group interchange causes deterioration of performance, a bank deallocation can be also executed. As this criterion for determination, it is possible to employ a policy that a bank is deallocated when a capacity of a bank including an erroneous sub-bank is equal to or less than a predetermined rate of all the memory capacity and an interleaving factor is less than the interleaving factor of an interchange partner after the bank deallocation.

Abstract: A multi-nodal data processing system in which each node has a local memory for storing message send vectors, one for each other node in the system. When a node has a message to send, it places the message in the message send vector corresponding to the destination node of that message. When a node is ready to receive messages, it reads messages from the message send vectors corresponding to this node in the other nodes. Each message send vector has a head pointer and a tail pointer for defining the head and tail of a queue of messages. Each tail pointer is held locally, in the same node as the message send vector to which it relates, while the head pointer is held in the destination node of that message send vector.

Abstract: A CD-ROM control chip is provided for a use of firmware information update in the CD-ROM system. The control chip at least includes a microprocessor, a decoder, a controller, and an extra memory. The microprocessor is coupled to a data bus, and further coupled to an external ROM, which stores all firmware information. The decoder is coupled to the microprocessor through the data bus, and is also coupled to an external buffer memory and an external main board interface. The external main board interface allows the CD-ROM control chip to communicate with an external computer. The controller is coupled to the decoder, and is coupled to the microprocessor the data bus. The controller is used to receive information and control signals from an external CD. The extra memory is coupled to the microprocessor through the data bus.

Abstract: Dynamic random access memory with variable configuration depending on the number and capacity of standard memory modules, of DIMM type plugged into a first plurality of slots of a memory motherboard comprising a control unit, into which it is possible to plug, into the first plurality of slots, in substitution for the memory modules, expansion supports, in turn provided with a second plurality of slots for the insertion of standard memory modules of DIMM type, and of column address latch registers each associated with a slot of the second plurality and thereby to support and allow the configurability and operability of interleaved-block memory, and access cycles, with partial time overlap, without renouncing the use of commercially available DIMM memory modules and without burdening the basic memory configuration with all the overheads required to support the interleaved-block configuration.

Abstract: There is disclosed a system and method for maintaining data coherency between a primary process controller operable to execute process control tasks and a backup process controller operable to replace the primary process controller upon failure, wherein the primary process controller cyclically executes the process control tasks during base control cycles having a period, T. The system comprises 1) a tracking circuit operable to detect changed data in a main memory in the primary process controller; 2) a data buffer for temporarily storing the changed data; and 3) data transfer circuitry for transferring the changed data in the data buffer to a backup memory in the backup process controller at least once during each base control cycle of the primary process controller, such that the transfer of changed data does not interfere with execution of the process control tasks.

Abstract: A method, system and computer program product in which half of the storage space on a non-volatile storage device is used to maintain a copy of the last "known-good" copy of the operating system and on invocation by a user, restoring from this backup copy when, for example, the operating system has become corrupted due to changes made to settings or device drivers.

Abstract: A system for detecting an initialization flag signal and distinguishing it from a normal flag signal having half the duration of the initialization flag signal. The initialization flag detection system may be included in the command buffer of a packetized DRAM that is used in a computer system. In one embodiment, the initialization flag detection system includes a pair of shift registers receiving the flag signal at their respective data inputs. One of the shift registers is clocked by a signal corresponding to an externally applied to command clock signal, while the other shift register is clocked by a quadrature clock signal. Together, the shift registers store a number of samples taken over a duration that is longer than the duration of the normal flag signal. The outputs of the shift registers are applied to a logic circuit, such as a NAND gate, that generates an initialization signal when all of the samples stored in the shift registers correspond to the logic levels of the flag signal.

Abstract: The present data storage subsystem includes a data stream optimization system that optimizes its data throughput performance for a particular type of data that is stored therein, such as video on demand data. The data stream optimization system manages the retrieval of the stored video data to more efficiently use the cache memory. This is accomplished by creating a data stream entry into a table for each viewer that requests access to a stored video file. The data stream optimization system also records the storage extent of each video file so that the identity of the next successive segment of the video file that is being accessed is known. The data stream optimization system monitors the amount of data stored in the cache memory for each of the data streams and identifies the next of these data streams that requires replenishment.

Abstract: A system and method for managing memory in a network. In a computer network in which multiple computers (nodes) are interconnected by a network, the primary memory on one node may be used to store memory data (pages)from other nodes. The transfer of a data page over the network from the memory of a node holding it to the memory of another node requesting that data gives improved performance when compared to the transfer of the same data from disk, either local or remote, to the requesting node. Global information about the disposition of the nodes and their memories in the network is used to determine the nodes in the network that should best be used to hold data pages for other nodes at a particular time. This information is exchanged by the nodes periodically under command of a coordinating node.

Abstract: A storage medium has at least one diffraction grating. The diffraction grating is formed as a holographic interference fringe pattern. The pattern is formed as it two-dimensionally diffracts an incident light beam in a plurality of directions or one-dimensionally diffracts an incident light beam in a direction. A combination of such patterns and also a plurality of rows of such patterns on the storage medium are available. A light beam is radiated to the storage medium. The light beam diffracted in the direction(s) is detected by a photodetector, such as a CCD device, that generates a signal carrying data stored as the holographic interference fringe pattern. The signal is then decoded by a processor to reproduce the data.

Abstract: Within a content addressable memory, the latency in a memory access is reduced by combining the steps of effective address generation addition and searching within the content-addressable memory. Two inputs to the content-addressable memory are conditioned and then supplied to matching cells, which determine which address stored in the content-addressable memory will be output. This is accomplished without a full adder being implemented to add the two input operands before being supplied to the content-addressable memory.