Abstract: Apparatus having a multi-way cache (18), the apparatus including a first user controllable element (102, 104, or 106) having a predetermined first attribute corresponding to a first way of the multi-way cache; a second user controllable element (102, 104, or 106) having a predetermined second attribute corresponding to a second way of the multi-way cache; a conductor (87) for transferring an access attribute to the multi-way cache; first compare circuitry (60) which compares the access attribute to the predetermined first attribute to provide a first comparison result; second compare circuitry (60) which compares the access attribute to the predetermined second attribute to provide a second comparison result; first way control circuitry (92) for selectively enabling the first way of the multi-way cache based on the first comparison result; and second way control circuitry (92) for selectively enabling the second way of the multi-way cache based on the second comparison result.

Abstract: A file management apparatus is used in an information processor using a media exchange type storage device including a plurality of storage media, at least one data access device, and a storage media exchanging means as an external storage device. The file management apparatus includes a data block management device for dividing storage regions of the respective storage media into data blocks of fixed capacity and managing the use states of the divided data blocks. A data block allocation device allocates unused data blocks shown by the data block management device to a file to which a writing request from the information processor has been given.

Abstract: A method and apparatus for arbitrating access requests to a memory is accomplished which allows for the serialization of the memory access requests, when a memory access collision is detected. A memory access collision is detected when contemporaneous accesses to an identical memory block of the memory occur. Processing begins when a plurality of operations are received via a plurality of parallel pipelines, wherein at least some of the plurality of operations require memory access. The plurality of parallel pipelines are then monitored for memory access collisions. At least some of the plurality of pipelines are then serialized when a memory access collision is detected to ensure proper processing order of the plurality of operations involved in the memory access collision.

Abstract: Methods of allocating, writing, reading, de-allocating, re-allocating, and reclaiming space within a nonvolatile memory having a bifurcated storage architecture are described. A method of reliably re-allocating a first object includes the step of storing a location of a first object in a first data structure. A location of the first data structure is stored in a second data structure. A duplicate of the first object is formed by initiating a copy of the first object. An erase of the first object is initiated. A write of a second object to the location of the first object is then initiated. The duplicate object is invalidated. The status of copying, erasing, and writing is tracked. The copy status, erase status, write status, and a restoration status are used to determine a recovery state upon initialization of the nonvolatile memory. The duplicate object is invalidated , if the writing status indicates that the writing of the second object has been completed.

Abstract: A method of managing and speculatively issuing architectural operations in a computer system is disclosed. A first architectural operation at a first coherency granule size is issued and translated into a large-scale architectural operation. The first architectural operation can be a first cache instruction directed to a memory block, and the translating results in a page-level cache instruction being issued which is directed to a page that includes the memory block. The large-scale architectural operation is transmitted to a system bus of the computer system. A system bus history table may be used to store a record of the large-scale architectural operations. The history table then can be used to filter out any later architectural operation that is subsumed by the large-scale architectural operation. The history table monitors the computer system to ensure that the large-scale architectural operations recorded in the table are still valid.

Abstract: A recording system such as a magnetic tape data recording and reproducing system is arranged to record data management information to three different storage devices. The recording system records management information on a record medium such as a tape, a cassette memory built in a tape cassette and a recorder memory of the recording system. A control section of the recording system first reads the management information from the cassette memory, further reads the management information from the recorder memory if the management information of the cassette memory is insufficient, and finally reads the management information from the record medium if the management information of the recorder memory is still insufficient.

Abstract: One or more sets of one or more cache lines of cache locations of an apparatus, such as a processor, a system embedded with a processor, and the like, are dynamically operated at the same or different time periods as different register sets to supply source operands and to accept destination operands for instruction execution. The different register sets may be of the same or of different virtual register files, and if the different register sets are of different virtual register files, the different virtual register files may be of the same or of different architectures. The cache locations implementing the registers may be directly accessed using cache addresses or content addressed using memory addresses.

Abstract: A method allows manipulation of disk partitions defined by an IBM-compatible partition table. The disk partitions may be located on one or more disks attached to one or more disk drives. Each partition has an associated file system type, such as FAT or HPFS. An interrupted manipulation may be resumed at a point in the progress of the manipulation near the point of interruption. Available manipulations include verifying the integrity of a partition's file system structures; displaying information about a partition; moving a partition to a different location; resizing a partition; and converting a partition from one file system to another file system. The resizing step is illustrated with particular reference to HPFS file systems and FAT file systems. The details required to perform these manipulations are attended to by an implementing program that requires only general direction from a user.

Abstract: A method and apparatus for arbitrating requests for access to a single buffer memory embedded within a disk drive in which a disk data channel is assigned a highest priority for buffer access within a queue. An arbitration cycle progressively services access requests pending within the queue, beginning with providing buffer access to the disk data channel and following with accesses to other channels during an arbitration cycle completion interval in accordance with a round-robin circular priority arrangement providing orderly access to all channels contending for memory access. At the end of completion interval, buffer access returns to the disk data channel, and thereafter, the arbitration cycle is repeated.

Abstract: Write posting buffers and read prefetch buffers are arranged in an integrated multiport switch between a PCI interface and an external memory interface. When a PCI host initiates a PCI transaction to write data from an external memory, the data provided by the PCI host is written into the write posting buffers. Then, the contents of the write posting buffers is transferred to the external memory. The read prefetch buffers are used to temporarily store data prefetched in anticipation of a PCI transaction initiated by the PCI host to read that data from the external memory. When the PCI host initiates the read transaction, the address of the requested data is compared with the address of the prefetched data to transfer the prefetched data to the host if a match is detected. In an auto-prefetch mode, data is automatically prefetched from the external memory when an extension bus port output queue contains a frame pointer for a frame queued for transmission over the PCI interface to the PCI host.

Abstract: An optical head is provided for transmission of light between a source of light and a storage location along an optical path that includes at least one offset optical element.

Abstract: A method and apparatus for processing pipelined command packets in a packefized memory device. The command packets are initially stored in one of several command units, and the commands are subsequently coupled to a common command processor for execution. The command units each include a latch for storing a command packet, a counter, and a start command generator. The counter is preloaded with a count corresponding to the timing that the command is received at a location within the memory device. The counter begins counting responsive to a flag bit received with the command packet. The start command generator receives the count of the counter, and decodes different counts depending on the type of command (e.g., a “read” or a “write”) and the speed of a clock signal that is used to control the operation of the memory device. When the start command generator decodes a count, it latches command bits of the applied command packet and generates a start command signal.

Abstract: A memory cache method and apparatus with two memory execution pipelines, each having a translation lookaside buffer (TLB). Memory instructions are executed in the first pipeline (324) by searching a data cache (310) and a prefetch cache (320). A large data TLB (330) provides memory for storing address translations for the first pipeline (324) A second pipeline (328) executes memory instructions by accessing the prefetch cache (320). A second micro-TLB (340) is associated with the second pipeline (328). It is loaded in anticipation of data that will be referenced by the second pipeline (328). A history file (360) is also provided to retain information on previous instructions to aid in deciding when to prefetch data. Prefetch logic (370) determines when to prefetch data, and steering logic (380) routes certain instructions to the second pipeline (328) to increase system performance.

Abstract: A recovery mechanism to eliminate the need to re-fetch cache entries during virtual-to-physical memory re-mapping by reducing accesses and thus the demand on the table lookaside buffer (TLB) during the re-mapping recovery. Once one data block in a given page has been revalidated, the other blocks in the same page can be revalidated without accessing the TLB. If the virtual-to-physical mapping of one data block in a page has not changed, then the other data blocks within the same page also have not changed. Therefore, if a virtual tag was previously valid and a data block on the same page as the data block associated with the virtual tag has been revalidated, the virtual tag is valid and the virtual address can be validated. To identify which virtual tags are currently valid and which virtual tags were valid prior to the last re-mapping, a pair of valid registers is employed. A toggle circuit alternates between the valid registers.

Abstract: A method for programming a synchronous dynamic random access memory (SDRAM) device including a memory array is disclosed. In the method, the SDRAM device is initially programmed to have a first control operating option in response to a first command. Reprogramming of the SDRAM device includes a second control operating option in response to a second command. The array remains simultaneously active in response to an active internal row address signal while the control operation feature is programmed to have the second control operating option.

Abstract: A method and arrangement for maintaining a time order of entries in a memory determines a row in which the entry will be stored, the memory being logically divided into rows and columns. The columns are arranged sequentially in each row from the newest to the oldest. Once the row in which the entry will be stored is determined, the entry is stored in that row in the column (or entry location) that is the newest column. The entry that was previously in the newest column is shifted to the next older column, and the entry that was previously in the next older column is shifted to the next most older column, etc. If a row is completely filled prior to the writing of a new entry, then the entry in the oldest column is removed from the memory and the other entries shifted.

Abstract: A method and system for bypassing command pipelines in a pipelined memory command generator is used whenever commands must be generated with a latency that is shorter than the latency at which commands can be generated using the command pipelines. The timing of commands issued by the command pipelines is a function of a digital word, and the digital word therefore indicates the latency of the command generator. When the digital word corresponds to a latency that is shorter than the latency at which the command pipeline can generate commands for read and write operations, a bypass circuit—rather than the command pipeline—generates the commands. The bypass circuit is capable of generating the commands with a latency that is shorter than the latency at which the command pipeline is capable of issuing the commands. In addition to issuing the commands, the bypass circuit generates an inhibit signal to prevent the command pipelines from generating duplicate commands.

Abstract: A duplexing system and method for writing a back-up list in which a back-up process is substituted for a process having an error while performing plural processes. Memory space to store a back-up order list is allotted to two bytes per process. A number of the leading order process is stored in the first byte, whereas a number of following order process is stored in the second byte. Further, the top priority bit or the last bit of each byte of memory space in which the process to be backed-up is allotted is set, and thus the existence of a registration is displayed. Further, if error an occurs at plural processes, a non back-up process generates a back-up order list according to time sequence of error generation. If an error occurs at a process of another top priority order while operating a back-up of a back-up process, the process is registered at the leading order list.

Abstract: A command buffer for use in packetized DRAM includes a four stage shift register for shifting for sequentially storing four 10-bit command words. The shift register combines the four 10-bit command words into a single 40-bit command word and transfer the 40-bit command word to a storage register for processing by the DRAM. The shift register may then continue to receive and store subsequent 10-bit command words. The command buffer also includes circuitry for determining whether a command packet is intended for the memory device containing the command buffer or whether it is intended for another memory device. Specifically, a portion of the 40-bit command word from the storage register is compared to identifying data stored in an identifying latch. In the event of a match, a chip select signal is generated to cause the memory device to perform the function corresponding to other portions of the 40-bit command word.

Abstract: A method for exchanging information within a mesh network that has an array of nodes defined by four quadrants. The method includes the initial step of exchanging information from a set of nodes in one quadrant to a set of nodes located in an adjacent quadrant. The exchange of information simultaneously occurs in both a vertical and horizontal direction within the array. Information is then exchanged between nodes within the same quadrant and subquadrants.