Abstract: A method, apparatus, and article of manufacture for asynchronously writing and reading multiple data streams is disclosed. The method comprises the steps of writing a plurality of data sub-streams into shared memory buffers asynchronously and in parallel using a write process for each data stream, reading the plurality of data sub-streams from the shared memory buffers asynchronously and in parallel using a read process for each data sub-stream, and writing the data sub-stream into the storage device. Data passing between the write processes and the read processes are stored in a plurality of shared memory buffers, with access to the shared memory buffers controlled by semaphores.

Abstract: Within a content addressable memory, the latency in a memory access is reduced by combining the steps of effective address generation addition and searching within the content-addressable memory. Two inputs to the content-addressable memory are conditioned and then supplied to matching cells, which determine which address stored in the content-addressable memory will be output. This is accomplished without a full adder being implemented to add the two input operands before being supplied to the content-addressable memory.

Abstract: A parallel processing system in which access contention of a read cycle from a processing unit side to a local shared memory and a write cycle from a shared bus system side on the local shared memory is reduced and a memory LSI which may be used in such unit are provided. The parallel processing system comprises a local shared memory between the processor and a shared bus. Address and data input means (WA and DI) for writing data to a memory cell and address input means (RA) and data output means (DO) for reading data are provided independently from each other to parallelize operations for reading from the processor side and for writing from the shared bus side.

Abstract: A storage medium has at least one diffraction grating. The diffraction grating is formed as a holographic interference fringe pattern. The pattern is formed as it two-dimensionally diffracts an incident light beam in a plurality of directions or one-dimensionally diffracts an incident light beam in a direction. A combination of such patterns and also a plurality of rows of such patterns on the storage medium are available. A light beam is radiated to the storage medium. The light beam diffracted in the direction(s) is detected by a photodetector, such as a CCD device, that generates a signal carrying data stored as the holographic interference fringe pattern. The signal is then decoded by a processor to reproduce the data.

Abstract: To avoid multiplexing within the critical address path, the same field from an address is employed to index rows within a cache directory and memory regardless of the size of the cache memory. Depending on the size of the cache memory being employed, different address bits (such as Add[12] or Add[25] are employed as a "late select" for the last stage of multiplexing within the cache directory and cache memory. Since smaller address tag fields are employed for the larger cache memory size, the extra address tag bit is forced to a logic 1 within the cache directory and compared to a logic 1 by address tag comparators at the output of the cache directory.

Abstract: A read enable signal OEMF activated in response to an input command is applied to an N minus 2 clock shift circuit included in an output control circuit for implementation of ZCAS latency. An output signal of the N minus 2 clock shift circuit and an internal mask instructing signal activated in response to an external mask instructing signal are logically processed and applied to a one-clock shift circuit. According to an output signal OEMQM of one-clock shift circuit, a data output enable signal OEM controlling activation/inactivation of an output buffer circuit is activated/inactivated. Data output controlling portion occupying area of a synchronous dynamic random access memory is reduced and timings of activation/inactivation of data output by different commands are made the same.

Abstract: An arbitration and task switching technique in a real-time multiprocessor data processing system (20) having a common bus (32) and a segmented shared memory (30), where fullness of memory segments of the shared memory (30) is used as a measurement for arbitration and task switching priorities. A bus request mechanism in each of the processors dynamically calculates normalized priority values based on relative needs across the system (20). The normalized priority calculation is based on monitoring the fullness of memory segments of the shared memory (30) associated with each processor (24, 26, 28) of the system (20). Using this normalized priority calculation, the bus access order and bus bandwidth are optimally allocated according to tasks executed by the processors (24, 26, 28). Also, the normalized priority calculation and a preprogrammed threshold is used to control task switching in the multi-processor system (20).

Abstract: A multi-level cache and method for operation of a multi-level cache generating multiple cache system accesses simultaneously. Each access request includes an address identifying a memory location having data that is a target of the access. A insertion pointer inserts each access request into an entry in a memory scheduling window. Each entry is marked as valid when that entry is ready to be applied to a first cache level. A picker picks valid entries from the memory scheduling window by pointing to the picked entry and applying the address therein to the first cache level. The picking occurs in a free-running mode regardless of whether the accesses hit in the first cache level. A second cache level receives accesses that have missed in the first cache level. A resource monitor in the second cache level determines when a predetermined number of resources are committed to servicing the accesses that have missed in the first cache level.

Abstract: A semiconductor memory device has a memory space which includes blocks and each of the blocks includes sectors. The sectors have a data storing region and a flag region. Data stored in a sector is marked as valid or erased, depending on the flags in the flag region. If an even number of the flags in the flag region have a logical value of 1, the data is considered to be erased. The data in each sector may be erased and unerased a number of times, by sequentially altering the value of the flags in the flag region. Data stored in the memory may be erased on a sector-by-sector basis.

Abstract: The present invention provides a method for selectively reclaiming fragmented space on a multiple volume cartridge (MVC) device using a cost-benefit type analysis to determine whether making the fragmented space useable justifies moving all nonexpired data volume sets to another MVC. The present invention analyzes the allocation of space on the MVC to determine the location and size of any gaps between nonexpired data volume sets. Any gaps appearing at the end of the MVC are automatically reallocated for subsequent use. Any gaps appearing between nonexpired data volume sets are analyzed to determine whether the size and location meet predetermined criteria before moving any of the nonexpired data volume sets. In addition, the present invention allows selective movement of less than all of the nonexpired data volume sets if the size of the separating gap is larger than any nonexpired data volume sets appearing after the gap.

Abstract: In accordance with the preferred embodiment of the present invention, a first-in-first out queue includes a buffer for storing data. A write pointer indicates a next position for data to be written into the buffer from an external interface. An input pointer indicates a next position for data to be read out to processing circuitry. An output pointer indicates a next position for data which has been processed by the processing circuitry to be returned to the buffer. A read pointer indicates a next position for data to be read out of the buffer to the external interface.

Abstract: An interface and method for a synchronous DRAM (syncDRAM) memory are provided that improve performance. The read operation in a syncDRAM is significantly sped up by eliminating the step of opening a new page of data in a SyncDRAM using a speculative read method. This provides the ability to open a page of information in the SyncDRAM with a command generator in response to a data request. Speculative read logic is also included to continue reading from the page with an invalid address until a second read request occurs. Thus, in the event that a subsequent read request occurs that requests data located on the same page as the prior request, the data can be indexed and read from a location on that page without having to first assert the SCS# and SCAS#. This frequently removes the step of opening a page from the read process and, over time, can significantly speed up the overall SyncDRAM reads in a computer system.

Abstract: A buffer circuit includes a buffer input, a memory, a memory controller and an upper buffer limit register. The memory is coupled to receive information from the buffer input. The memory has a single-port for accessing a plurality of storage locations for storing the information. The upper buffer limit register is for storing an upper buffer limit value. The memory controller is coupled to the memory and the upper buffer limit register. The memory controller prioritizes writes over reads when the number of storage locations of the memory storing the information is less than the upper buffer limit value. The memory controller prioritizes reads over writes when the number of storage locations storing the information is greater than the upper buffer limit value.

Abstract: A method for selecting a next command to execute from a set of SCSI commands where the commands are gracefully aged and performance of a disk drive is improved. An execution threshold age, a pool threshold age, and an age threshold age are used to determine what command is executed next. A mechanical time delay is calculated for a command based on the time required to position the read/write head over the data location requested in each command. A command age is calculated based on a current time and the time the command was received from the host. The command age is checked against the execution threshold age and pool threshold age. Any commands that have aged beyond the execution threshold age are executed. If the oldest command has aged beyond the age threshold age, then any command that has both aged beyond the pool threshold age and has the smallest mechanical time delay is executed, otherwise the command with the smallest mechanical time delay is executed.

Abstract: A method and apparatus for merging multiple misses to a multi-level cache is provided to improve the performance of the cache. A first and second non-blocking cache are each provided with miss queues storing entries corresponding to access requests not serviced by the respective caches. The first and second miss queues have an indicator associable with each of said entries in the respective miss queues indicating that the entry is a primary reference to data located at the address associated with said entry. If a subsequent instruction generates a cache miss accessing data associated with an entry in a miss queue, the subsequent miss is merged with the appropriate entry in the miss queue and serviced when the primary reference is serviced.

Abstract: A data storage system wherein a main frame computer section having main frame processors for processing data is coupled to a bank of disk drives through an interface. The interface includes a bus having: an bus-select/address/command portion; bus-grant/data/clock-pulse portion; a bus queue portion; and an ending-status portion. A plurality of addressable memories is coupled to the bus. A plurality of controllers is coupled to the bus. Each one thereof being adapted: to assert on the bus-select/command/address portion of the bus, during a controller initiated bus select assert interval, a command. The addressed memory is adapted to produce on the queue portion of the bus a queue signal a predetermined time after a controller initiated bus select assert interval. The queue signal terminates the bus select interval. Another one of the controllers is adapted to provide on the bus-select/address/command portion of the bus another address and command after the queue signal terminates the bus select assert interval.

Abstract: A method of avoiding deadlocks in cache coherency protocol for a multi-processor computer system, by loading a memory value into a plurality of cache blocks, assigning a first coherency state having a higher collision priority to only one of the cache blocks, and assigning one or more additional coherency states having lower collision priorities to all of the remaining cache blocks. Different system bus codes can be used to indicate the priority of conflicting requests (e.g., DClaim operations) to modify the memory value. The invention also allows folding or elimination of redundant DClaim operations, and can be applied in a global versus local manner within a multi-processor computer system having processing units grouped into at least two clusters.

Abstract: A method and apparatus of selectively flushing a conflicted write transaction from a memory controller. According to the method, a new transaction is received that identifies a memory address to which the transaction is directed. It is determined whether an address of the new transaction matches an address of any previously queued transaction. When a match occurs, the one previously queued transaction that matches the new transaction is flushed from queue.

Abstract: In a memory composed of a plurality of banks, even if succeeding access is performed to the same bank as that being currently accessed, the succeeding access can be controlled according to the destination which is currently accessed and its accessed state. In addition, if particular relationships exist between a precedingly accessed destination and the succeedingly accessed destination, a corresponding main word line out of main word lines which correspond to respective rows of respective banks can be still held in its selected state even after the preceding access has been terminated.

Abstract: A method for modifying data to be used by a program of a data processing system, in particular a controller for controlling an assembly. The data is stored in a first memory in the form of reference data. The memory addresses of the reference data in the first memory are stored in a reference data memory address table in the first memory so that they can be accessed by the program. According to this method, the reference data memory address table is copied to a second memory in the form of a working data memory address table to be addressed by the program, and the reference data to be modified is copied to the second memory in the form of working data to be modified. Further, the working data memory address table is modified so that the memory addresses of the working data to be modified in the second memory replace the memory addresses of the reference data to be modified in the first memory, after which the working data is modified.