Abstract: A magnitude comparator suitable for use in a FIFO memory is modified to compare the magnitudes of two values more quickly. Bit comparators are divided into groups which generate compare output signals in parallel to one another, thereby reducing total magnitude comparator delay and resulting in faster operation. These compare output signals are fed into a control element which determines which compare output signal is allowed to pass through as the final compare output signal.

Abstract: An improved sample and hold signal generator produces very short delay intervals between successive sample-to-hold transitions that are both collectively and individually adjustable. A plurality of capacitors are charged to a precharge level upon the occurrence of a precharge signal and discharged to the threshold level of a plurality of amplifiers through a plurality of constant current sources upon the occurrence of a discharge signal. When the voltage on a particular capacitor is discharged to the threshold level, the associated amplifier produces a sample-to-hold signal transition and the voltage level of a signal being sampled is stored on a capacitor. In successive cells of the sample and hold generating means the threshold level is reached at incrementally varying delay times that are separated by approximately equal time intervals.

Abstract: A HTS switch includes a HTS conductor for providing a superconducting path for an electrical signal and an serpentine wire actuator for controllably heating a portion of the conductor sufficiently to cause that portion to have normal, and not superconducting, resistivity. Mass of the portion is reduced to decrease switching time.

Abstract: A sample-and-hold circuit includes a first switch element which is opened or closed in accordance with a first control signal so as to selectively connect an input signal terminal for receiving an input signal to an internal terminal, a non-linear element for connecting the internal terminal to an output terminal, a potential holding circuit connected between the output terminal and ground, and a second switch element or a current source circuit which is controlled by a second control signal so as to selectively connect the output terminal to ground.

Abstract: In a thyristor ignition circuit, a forward voltage drop occurring in a signal path of an anode and a gate of a thyristor is reduced. An anode of a thyristor of the thyristor ignition circuit is connected to one signal terminal, and a gate thereof is connected to another signal terminal. The thyristor ignition circuit further comprises a transformer having a primary winding for receiving an ignition signal, and a first secondary winding having one end connected to a cathode of the thyristor and the other end connected to the other signal terminal. The thyristor is ignited via the cathode in response to the ignition signal applied to the transformer. A signal path is established between one signal terminal and the other signal terminal through the anode-to-gate path.

Abstract: The device comprises a first path provided with an amplifier (1) amplifying in a first frequency band, and a second path provided with an amplifier (2) amplifying in a direction opposite to that of the first amplifier and in a second frequency band other than the first frequency band, a first filter element (L1) having a low pass characteristic for transmitting the signals of the first path, and a second filter element (C1) having a high pass characteristic for transmitting the signals of the second path. The two paths are combined by a third filter element (CA) having a high pass characteristic, arranged in series with a fourth filter element (LA) having a low pass characteristic, whose junction point is connected to ground by a matched impedance (ZCA), and a signal polarity inverting element (TA) is inserted in series between two of the filter elements.

Abstract: In a substrate potential generator, a substrate potential is supplied by a substrate potential supplier controlled by a substrate potential detector. The substrate potential detector sends a setting signal having a hysteresis characteristic relative to the substrate potential. That is, the setting signal is higher when the substrate potential supplier is stopped than when the substrate potential supplier is activated or when negative charges are injected into the substrate potential. Thus, the operation of the substrate potential supplier is stopped after the substrate potential becomes lower than the lower setting potential when the substrate potential supplier is activated, while the operation of the substrate potential supplier is started after the substrate potential becomes higher than the upper setting potential after the operation of the substrate potential supplier is stopped.

Abstract: An analog input is compared with a comparison value by an analog comparator to set a comparison result register and comparison is automatically repeated until the value of the register coincides with the value of an expected value storing register. When the both values coincide with each other, an interrupt request signal is outputted and comparison is completed.

Abstract: The present invention relates to a semiconductor storage device for executing an address multiplex method.

Abstract: A semiconductor IC device includes a memory cell group; a pair of bit lines connected to the cell group; plural equalization transistors T.sub.R connected between the bit lines; address transition detectors ATD for detecting changes in address bits; and plural equalizing pulse generating circuits composed of plural logical gates, 15 to 22, respectively and provided for each equalization transistor to generate an equalizing pulse signal to each equalization transistor so that the levels of the two bit lines can be equalized with each other. Since signals outputted from the address transition detectors are synthesized, in particular at a node to which the equalizing pulse signal is applied, the number of logical gate stages to synthesize the detector output signals can be reduced and the wire lengths (e.g. wire capacitances) of the logical gates can be well balanced, thus improving the equalizing speed of the IC device.

Abstract: A differential comparator with inputs switched and capacitively coupled to inverters which have capacitive cross-coupling feedback for a latching operation. The inverters also have direct switched feedback for autozeroing. The inputs further have a shorting switch between the input switches and the coupling capacitors for offset compensation. Complementary operation of the switches provides precharge and evaluation phases of operation. During precharge the inputs are applied to the input coupling capacitors and the inverters are autozeroed; during evaluation the inputs are transferred to the inverters through the coupling capacitors and the outputs feedback positively through the cross-coupling capacitors to latch the pair of inverters.

Abstract: A latch circuit has two initializing circuits that receive identical inputs and generate two identical output signals, one internal and one external. An inverter inverts the internal output signal to generate a complementary external output signal. One or more control signals can force the output signals to fixed states. When the control signals are inactive, the output signals depend on either an input signal or a feedback signal generated from the internal output signal, as selected by a selecting circuit.

Abstract: Gain linearity problems caused by impact ionization in a active MOS device are avoided by connecting an MOS shield device in series with the active MOS device so that the overall supply voltage is split across two devices, keeping both devices in a region of operation well below where impact ionization becomes a significant problem. The gate of the MOS shield device is maintained at a voltage proportional to its drain voltage, thereby keeping the device in the saturation mode and avoiding an abrupt mode change associated with prior art shield circuits.

Abstract: A plurality of differential amplifier circuits are supplied with respective potentials of a plurality of paired bit lines and subjects the potentials of the bit line pairs to the differential amplification. The plurality of differential amplifier circuits are connected to paired data lines. The paired data lines are connected at one end to a first clamping circuit for clamping the potential of the paired data lines. The first clamping circuit is connected to a common load circuit acting as a common load for the plurality of differential amplifier circuits. The paired data lines are connected at the other end to a second clamping circuit for reducing the amplitude of a voltage between the paired data lines.

Abstract: A high speed bipolar multiplexer circuit adds less than ten picoseconds delay to the data or test paths. The multiplexer circuit incorporates a low gain linear amplifier which is completely stable and compensates for any level losses through the input emitter followers. The minimal delay introduced in the system data paths and the good isolation between system data inputs and test data inputs matches the performance of the logic and memory circuits of the chips in which multiplexer circuits are incorporated.

Abstract: A solid state switch, with reverse conducting thyristors, is designed to operate at 20 kV hold-off voltage, 1500 A peak, 1.0 .mu.s pulsewidth, and 4500 pps, to replace thyratrons. The solid state switch is more reliable, more economical, and more easily repaired. The switch includes a stack of circuit card assemblies, a magnetic assist and a trigger chassis. Each circuit card assembly contains a reverse conducting thyristor, a resistor capacitor network, and triggering circuitry.

Abstract: An integrated dynamic amplitude limiter is disclosed for limiting the deviation of a transmitter operating at audio frequencies. In an amplitude limiter according to the invention, a dynamic AGC amplifier block (1), a level clipper block (3) and a block (2) which forms the higher and lower limiting levels are implemented using switched capacitors (SC), and they are formed into an integrated amplitude limiter circuitry, and the voltages which define the higher and lower limiting levels are formed from the voltage of the band-gap voltage reference (Vbgref), which voltage is formed in relation to the virtual ground voltage of the amplifier circuitry, in which case the limiting levels are independent of the supply voltage (Vdd).

Abstract: This invention relates to a capacitive switching network for producing signals of opposite polarity. In one embodiment of the invention, a first signal (V1) is applied to the first plate of a first capacitor (C1) and a second signal (V2) is applied to the first plate of a second capacitor (C2). The first plates of the first and second capacitors are then shorted together to produce a combined voltage (Vc). The generation of Vc causes an AC voltage equal to (Vc-V1) to be produced at the second plate of C1 and an AC voltage equal to (Vc-V2) to be produced at the second plate of C2. By way of example, for C1 equal to C2, there is produced a Vc equal to (V1+V2)/2. Furthermore, if V1 is greater than V2, a negative going AC signal equal to (VC-V1) is produced at the second plate of C1, and a positive going AC signal equal to (Vc-V2) is produced at the second plate of C2. The capacitive network of the invention is highly suited for use in high speed differential comparators.

Abstract: A scan flip-flop cell including a flip-flop, a feed-back path by which the output of the flip-flop can be controllably held, and a latch in the feedback path that allows the cell to store two bits of data simultaneously.

Abstract: A TTL/CMOS compatible input buffer circuit comprises a Schmitt trigger input buffer stage and a reference voltage generator. In the TTL mode, the reference voltage generator supplies a reference voltage having a level that forces the trigger point of the Schmitt trigger to a predetermined value. In the CMOS mode, the reference voltage generator is disabled and a voltage equal to the power supply voltage is provided to the Schmitt trigger. The input buffer circuit affords an enhanced input noise margin and minimizes DC power loss.