Abstract: The gate of a transistor Q1 serving as a selection transistor is connected to a word line and the source thereof is connected to a bit line BL. The gate of a transistor Q2 serving as a cell capacitor is connected to the drain of the transistor Q1 and the drain thereof is connected to a pulse generation circuit. Whether an inverted layer is formed in the channel region of the transistor Q2 or not is determined according to the stored data. An inverted layer is formed in the channel region of the transistor Q2 having data "1" stored as storage data. The source of the transistor Q2 is connected to the gate of a transistor Q3. The drain of the transistor Q3 is connected to a pulse generation circuit 11 and the source thereof is connected to the drain of the transistor Q1. The transistor Q2 having an inverted layer formed therein is turned on when a preset voltage is supplied from the pulse generation circuit 11 in the stored data reading operation, and in this case, the transistor Q3 is turned on.

Abstract: In a digital video signal recording/reproducing apparatus for recording digital VCR video and audio signals by using a rotary cylinder, for a video signal with a frame frequency fN of 30 Hz or 29.97 Hz, the rotating frequency of the cylinder is set to 2.5 times fN. On the other hand, for a signal with a frame frequency fP of 25 Hz, the rotating frequency of the cylinder is set to 3.0 times fP. As a result, as long as the cylinder diameters are identical, the relative speed of the tape and the head is the same for video signals of either frame frequency fN or fP.

Abstract: The detector applies an analog input signal through respectively positive and negative offset voltages to the inputs of two comparators, one of which produces a first output signal as the input signal passes beyond a predetermined minimum voltage in the positive going direction, and the other of which produces a second output signal when the input voltage exceeds a minimum predetermined value in a negative going direction. The input signal is also applied directly to the input of a third comparator the output of which produces a third signal each time the input signal crosses over zero voltage in a positive going direction. The first and second comparator output signals are applied to the reset and set terminals, respectively, of a first flip flop. The output of this first flip flop, and the output of the third comparator are applied through an AND gate to the set terminal of a second flip flop.

Abstract: An external position detector is mounted on a head arm that also carries a transducer for tracking a magnetic disk. When the head arm is moved at constant speed, the position detector produces an output signal that is periodic but has a measurable pitch error or pitch unevenness. The periodic output signal is measured to determine the pitch error, and an amount of compensation required to compensate for the measured pitch error is calculated. A value of the periodic output signal corresponding to the amount of compensation and therefore corresponding to an absence of pitch error is calculated, and a servo signal is recorded on the magnetic disk at a location corresponding to the calculated value of the periodic output signal. The pitch error is thereby fully compensated, and the servo signal is recorded with precision.

Abstract: An embodiment of the present invention is a high-side driver comprising a pair of differential input controls each of which are coupled to a pair of comparators having first and second thresholds set at Vddh-1.5 volts and Vddh-2.5 volts, respectively. A logic block in front of a set-reset flip-flop recognizes only signals on the dual-input control lines where one is less than the Vddh-1.5 volt threshold and the other exceeds the Vddh-2.5 volt threshold. If signals on either or both of the dual-input control lines are between Vddh-1.5 volts and Vddh-2.5 volts, the logic block will prevent a change of state of the flip-flop which controls a high-voltage switch transistor connected to a load. The high-side driver further includes an under-voltage lockout to prevent false operation of the high-voltage switch transistor during the initial power up phase.

Abstract: A comparator indicates the relative magnitudes of input and reference signals with improved immunity to noise signals. The comparator includes first and second transistors differentially connected to receive the input and reference signals. Third and fourth transistors connected in a latching relationship are responsive in first alternate half cycles of clock signals to the outputs from the first and second transistors to provide a regenerative action on these outputs. In first portions of the first alternate half cycles of the clock signals, a degenerative action is provided by fifth and sixth transistors respectively on the third and fourth transistors to prevent the third and fourth transistors from regenerating until the input difference voltage of these transistors has had time to increase relative to the input noise on these transistors. The fifth and sixth transistors may be provided with sizes corresponding to, or preferably sightly greater than, those of the third and fourth transistors.

Abstract: Drivers for field-controlled switches are powered and switched on and off by the same combined command and power signal which consists of a command signal modulated by a clock signal forming a command envelope including a train of clock pulses. The invention prevents power from being lost by refreshing power during the PWM low state, such that the command high state pulses need not be used for restoring power. Power and a command to a field-controlled driver is provided by a combined command power signal consisting in the on-state of clock pulses, the groups being a function of switch signal pulse width, and in the off-state of absence of clock pulses. During the off-state of the driver, power is refreshed. In addition, by integration the clock pulses a dead time occurs within the driver circuit, while the driver is being switched on with different time constants.

Abstract: A semiconductor memory circuit comprises a plurality of memory cells each connected to a corresponding word line and a corresponding pair of digit lines connected connected to a sense amplifier. Each pair of digit lines are connected to one pair of read bus lines, which are respectively connected to emitters of a pair of transistors forming a current-voltage converter. The semiconductor memory circuit also includes one buffer which comprises a first bipolar transistor having an emitter connected to one of the pair of read bus lines, and a second bipolar transistor having an emitter connected to the other of the pair of read bus lines. Bases of the first and second bipolar transistors are connected to each other, and emitters of the first and second bipolar transistors are connected to different current sources, respectively. Collectors of the first and second bipolar transistors are connected being respectively connected to the emitters of the pair of transistors of the current-voltage converter.

Abstract: A coding circuit forming a 1-from-N code from an X-from-N code includes partial circuits in which each position of the X-from-N code forms an input value of a partial circuit. Each partial circuit is formed of three emitter-coupled transistor pairs, a current source connected to reference potential, level shift circuits, signal outputs and a symmetrical signal input. Each partial circuit is connected to the partial circuit with the next higher position of the X-from-N code as an input value and to the partial circuit with the next lower position of the X-from-N code as an input value.

Abstract: A floppy disk drive (FDD) includes a writable non-volatile memory which stores information indicative of a correction amount due to a difference between the reference position of a medium for the FDD and the position of an index detected by an index sensor and a digital delay circuit for deciding an adjustment time by producing an index signal which is provided by delaying the index detection pulse supplied from the index sensor by a count value corresponding to the correction amount supplied from the non-volatile memory. The index adjustment pulse is delayed by the count value so that the relative positions of indices of several FDD's can be made coincident with each other.

Abstract: The magnitude of successive peaks in a time varying electrical signal are measured by applying the signal to magnitude circuitry capable of providing an output related to signal magnitude. The circuitry has a first state during which the output is dependent of changes in signal magnitude and a second state during which the output is substantially independent of such changes. The circuitry enters the first state during a first time interval within which a first peak is applied to the magnitude circuitry, and during a second time interval within which a second peak is applied to the magnitude circuitry. During a third time interval intermediate the first and second time intervals, the circuitry enters the second state. The magnitude circuitry's output during the second time interval is independent of its output during the third time interval so that successive outputs of the circuitry are related to the respective magnitudes of said successive peaks.

Abstract: An all CMOS voltage comparator circuit which incorporates a strobed latch. A strobe signal precharges the entire circuit to a known state which is independent of the input voltages and in which substantially no static current is drawn. Under static conditions after the circuit has been strobed, the source coupled pair is virtually disconnected from the supply voltage(s) and draws almost no current, as well. When the circuit is strobed, a source coupled FET pair amplifies the differential input signal, with positive feedback provided through a pair of cross coupled PMOS load transistors, as well as cross coupled NMOS cascode transistors. The source coupled pair feeds a pair of output buffers, or drivers, whose FETs are sized such that a "low" voltage level is generated on both outputs until the source-coupled pair resolves the input voltage difference (i.e., the differential input voltage exceeds the switching threshold). At that time, the outputs become complementary digital levels and are usable.

Abstract: A servo control method in the absence control signals is comprised of a compare routine (L1) and a non-signal phase control routine (L2). The compare routine (L1) is carried out in such a manner that an envelope value detected by controlling a capstan motor is compared with a predetermined value, when the control pulse is not detected. The non-signal phase control routine (L2) is carried out in such a manner that the phase of the capstan motor is adjusted until a desirable state of video signals arrives by making a dummy phase error section generate a dummy phase error signal when the detected envelope value is smaller than the predetermined value. According to the present invention, a normal picture can be maintained even when no control signals are detected from the tape.

Abstract: A peak clipper according to this invention contains a differential circuit composed of a first and second p-n-p transistors, the first transistor's base terminal receiving the input signal and the second transistor's base terminal receiving a reference voltage for determining a clipping voltage to clip the input signal at a specified voltage level Connected to the collector of the second transistor is a current mirror circuit composed of a third and fourth n-p-n transistors. The current path of the current mirror circuit is connected to the base of a fifth n-p-n transistor, whose emitter is connected to the base of the second transistor. The reference voltage is changed so as to boost the current driving capability of the second transistor at the beginning of the switching operation at the differential circuit.

Abstract: In a belt-driven tape cartridge of the type used to store data on a magnetic tape in a high speed data storage and retrieval system, the tape must be maintained at a proper tension within the cartridge so as to maintain the tape taut against the write/read head. Slackness in the tape occurs after a repeated number of changes in the tape transport direction or start/stop events, because the tension experienced by the tape is not the same in both transport directions. In a belt-driven cartridge, the tape tension cannot be directly monitored. A method and apparatus for maintaining tape tension in a belt-driven cartridge are disclosed wherein tape tension is indirectly monitored by non-mechanically monitoring a selected tape characteristic, the characteristic changing as the tape tension changes.

Abstract: A Monolithic Microwave Integrated Circuit (MMIC) for capturing transients in the GHz range is disclosed. The device includes a transmission line formed in a GaAs substrate. The transmission line includes a number of threshold devices forming shunts on the transmission line. The threshold devices are positioned at predetermined locations with respect to one another. A reference signal and an unknown signal are counter-propagated along the transmission line. When the two signals collide, they produce a collision voltage which exceeds the threshold voltage of the threshold devices. The voltage information is distributed along the predetermined length of several threshold devices. Thus, amplitude, phase, and timing information regarding the two signals may be obtained. This information may be utilized for triggering, clock interpolation, data demodulation, and other applications.

Abstract: A programmable voltage comparator having a programmable hysteresis function controlling the comparator's output relative to first and second comparator input voltage variables. The programmable voltage comparator comprises an inverting and non-inverting input for receiving a first and second input voltages and an output providing a logic state signal reflecting the amplitude of the inverting and non-inverting input voltages. The comparator includes level shift circuitry coupled to the inverting and non-inverting inputs for programmably shifting the amplitude of the voltages applied to the inverting and non-inverting inputs responsive to the logic state output of the comparator. In one embodiment, the comparator includes a differential amplifier having inverting and non-inverting outputs, wherein the level shift circuitry comprises a first level shift circuit coupled to the non-inverting voltage input and having a feedback element coupling to the non-inverting output.

Abstract: A superconducting non-linear device comprising a superconducting conductor, a current source associated with the conductor for applying to the conductor a bias current, and a control device associated with the current source for selectably varying the bias current between a first value below the critical current for the conductor means and a second value above the critical current. The non-linear device is a switching device comprising a switching element in the form of a superconducting film, a terminal for inputting a signal to the switching element, a terminal for outputting a signal from the switching element, and a circuit for applying a DC bias current to the switching element and for causing the DC bias current to vary between a first value below the critical current for the superconducting film and a second value above the critical current.

Abstract: Auto-zeroing clocking signals, a first auto-zeroing clocking signal of comparatively-low frequency and duty cycle and a second auto-zeroing clocking signal of the same comparatively-low frequency but complementary and comparatively-high duty cycle, and a sampling clocking signal of comparatively-high frequency respectively initiate auto-zeroing of a circuit element subject to output offset error and data sampling of an A.C. input signal to a latch. The sampling of the A.C. input signal to the latch occurs at the comparatively-high frequency of the clocking signal during the "on" time of the comparatively-high duty cycle second auto-zeroing clocking signal of comparatively-low frequency enabling thereby to provide higher speed sampling than heretofore possible.

Abstract: A method for specifying characteristics of an integrated circuit wherein complementary output signals of the integrated circuit are required to cross or equal one another within a signal transition box during transitions of the complementary output signals. The signal transition box is defined by a maximum output signal level as a high side, a minimum output signal level as a low side, a minimum delay time as a leading side and a maximum delay time as a trailing side. A maximum allowable slew rate preferably is also defined.