Abstract: Zero cross detection accuracy is improved by providing one input side of a differential amplification circuit with a first voltage shift means for shifting the voltage of a signal to be detected up to the residual voltage value of the differential amplification circuit or more and the other input side of the circuit with a second voltage shift means having the same characteristic as the first voltage shift means and whose input terminal voltage is fixed to zero volt.

Abstract: A monolithic interface circuit for use with a linear variable differential transformer (LVDT) position transducer. The interface circuit includes a drive circuit for providing an excitation signal of selectable frequency and amplitude to the LVDT primary winding. The interface circuit further includes a decoder responsive to signals induced in the LVDT secondary windings for computing the position p of the LVDT core as a solution to the equation p=K(A-B)/(A+B), where A and B represent the signals induced in the primary winding and K is a constant scale factor. The decoder includes circuitry for rectifying and filtering the secondary signals, a charge balance loop responsive to the detected signals for providing a binary signal having a duty cycle representative of B/(A+B), and an output circuit responsive to the binary signal for providing the position output. The decoder provides excellent scale factor stability and linearity and is relatively insensitive to variations in primary drive amplitude.

Abstract: A data output circuit for a semiconductor integrated circuit device for outputting a data signal in sync with an output enable signal externally supplied, including: a comparing circuit for comparing a first data signal being outputted presently with a second data signal to be outputted next, when the data signal to be outputted is changed, and judging whether the first and second data signals are the same or different; a first output circuit for temporarily turning off output transistors and outputting the second data, if the comparing circuit judges that the first and second data signals are different; and a second output circuit for outputting the second data signal without turning off all the output transistors, if the comparing circuit judges that the first and second data signals are the same.

Abstract: A CMOS-compatible peak detection circuit includes a differential amplifier stage (10), an active peak holding circuit (12), and a passive peak holding circuit (14). The differential amplifier stage (10) produces an amplifier output signal that is responsive to the difference between an input signal being monitored and feedback from the active peak holding circuit (12). Both the active peak holding circuit (12) and the passive peak holding circuit (14) store a charge representing a voltage level that is indicative of the peak amplitude of the amplifier output signal during a time interval, the time interval occurring while a disable signal is inactive. The active peak holding circuit (12) provides the maximum value signal as feedback to the differential amplifier stage (10). The passive peak holding circuit (14) provides a max signal output corresponding to the maximum value to a voltage follower stage (16) that makes it available as an output when a readback enable signal goes active.

Abstract: A synchronized, digital sequential circuit includes state-controlled memory elements, each having a clock input, at least two outputs being complementary to one another and at least two inputs, which are connected to a logical OR linkage or wired OR connection. At least two state-controlled memory elements are connected in series. A first memory element performs the OR linkage or operation and a second memory element performs the AND linkage or operation of a combinatorial logic function. The settling time of a memory element and the delay time for forming the OR and AND linkages or operations coincide. Therefore, a high speed of operation is possible in the sequential circuit.

Abstract: A magnitude comparator suitable for use in a FIFO memory is modified to compare the magnitudes between any binary number and a fixed value. Bit comparators are divided into groups which generate compare output signals in parallel to one another, thereby reducing total magnitude comparator delay and resulting in faster operation. These compare output signals are fed into a control element which determines which compare output signal is allowed to pass through as the final compare output signal.

Abstract: An arrangement of a word line driver stage for semiconductor memory device is disclosed. The present invention is characterized in that a word line driver stages are into several sub-stages WD11-WD51 within a memory cell array, and each word line extending from a first one or a second one of the sub-stages is alternatively coupled to the sub-stage adjacent thereto. Thus this arrangement is capable of reducing the signal transmission delay and eliminating the adverse factor in the current critical design rule and layout.

Abstract: A power saving impedance transformation circuit for receiving a d-c biased signal comprises a junction transistor connected to operate as an emitter follower, means for connecting the base of the transistor to receive the signal, an operational amplifier having both inverting and non-inverting inputs, a first resistor connected between the emitter of the transistor and the operational amplifier inverting input, a second resistor equal to the first resistor in resistance and having one end connected to the operational amplifier inverting input, resistive means for connecting the other end of the second resistor to a first voltage source of a polarity which, in cooperation with the signal, forward biases the emitter-base junction of the transistor, the emitter-base junction of the transistor receiving its forward bias from the first voltage source exclusively through the first and second resistors and the resistive means, and means for connecting the collector of the transistor to a second voltage source of a p

Abstract: This invention relates to the MOS analog multi-bit comparator amplifier for performing the high speed digital multi-bit comparator function which is required, for example, in Cache Tag Random Access Memory of a computer system, and to the MOS analog XOR amplifier for performing the digital XOR function. The MOS analog comparator provided comprises N number of MOS analog XOR means for performing the digital XOR function and a MOS analog NOR means for performing the digital NOR function.

Abstract: In a phase shift circuit apparatus, first and second currents, produced by dividing signal current at a predetermined ratio by a variable bias voltage, are respectively supplied to fifth and eighth transistors which constitute the second differential amplification means, and the first and the second currents are respectively divided at predetermined ratios to supply currents, including square components; third, fourth, fifth and sixth currents which are caused to flow through fifth and sixth transistors of the third differential amplification means and seventh and eighth transistors of the fourth differential amplification means, respectively. Seventh and eighth currents which, produced by dividing signal current at predetermined ratios, are supplied to the ninth and the tenth transistors or the eleventh and the twelfth transistors from the first and the second connection nodes, respectively.

Abstract: An analog feedback rank order filter electronic circuit for receiving a number N of analog input signals (V.sub.1, V.sub.2, . . ., V.sub.N) and reproducing at its output (V.sub.o) the magnitude of that one of the input signals having a magnitude which is the K.sup.th largest among the magnitudes of the N input signals, K being an adjustable rank parameter in the range of 1 to N, comprising: N comparator subcircuits, a summation subcircuit, an integrator subcircuit and means for generating a control signal whose magnitude selects the desired rank parameter K.

Abstract: A zero-crossing detector for asynchronous detection of threshold transitions in a digitally sampled signal waveform. The Asynchronous Digital Threshold Detector (ADTD) receives a digitized self-clocking data readback waveform and provides the relative location of a zero-crossing within the sample period where it occurs. The digital output, which is useful for recovering data and clock signals, is in a digital form that can be used directly by a certain class of asynchronous digital phase detector systems. The ADTD is entirely digital and can be embodied in a low power configuration using CMOS technology.

Abstract: A track and hold circuit for producing an output voltage having a level related to the voltage level of an input voltage fed to the circuit during a track mode and for maintaining the level of the output voltage constant during a hold mode. The circuit includes a current source and a capacitor with the capacitor being charged with the current or discharged selectively in accordance with the level of the input voltage relative to the level of the output voltage to produce at the capacitor the voltage related to the voltage level of the input voltage. Current from the current source is directed away from the capacitor during the hold mode in order to reduce the effect of charge stored during the track mode from slowing the transition from track mode to hold mode operation.

Abstract: A comparator comprises transistors to turn on/off an input terminal and a control circuit to enable the transistors in a high impedance input state. The high impedance input state can be detected by the above construction without additionally providing any wire and connector.

Abstract: A dual-port memory device provides bit lines having a crossover pattern to reduce stray end coupling capacitances. Such crossover occurs approximately in the middle of the memory array for the device. Data in one-half of the array is stored in an inverted manner from data in the other half of the array. A preferred technique for clearing a memory provides for resetting only a portion of the bits of the array for each entry, with the bits of all memory entries being reset simultaneously. In order to provide such a reset function with the preferred bit line crossover scheme, a voltage node used for reset must also provide signal lines which are crossed over in the middle of the array.

Abstract: The present invention provides a high speed, all CMOS comparator utilizing positive feedback and DC voltage clamping. The circuit comprises two source-coupled PMOS transistors with their sources coupled to a current source or a supply voltage. A third PMOS transistor is coupled between the source of the first PMOS transistor and a terminal of a current mirror. The gate of this third PMOS transistor is coupled to the output node in such a way as to provide positive feedback to the circuit. As the negative input voltage becomes lower than the positive input voltage, the current passing through the second PMOS transistor increases and the current passing through the first PMOS transistor decreases. As the output node increases in voltage, the equivalent resistance of the third PMOS transistor increases, thus decreasing the current through the first PMOS transistor. This acts to increase the current being provided to the output node and increases the drive characteristics of the circuit.

Abstract: Process, voltage, and temperature variations affect the noise generation of an output buffer. Controlling the switching speed of the buffer over these variations also controls the buffer noise, which may be due to ground bounce or other reasons. In one prior-art technique, the current flow behavior of a static circuit is used to control the rise and/or fall times of the output buffer. However, accounting for all possible variations in the factors that influence the switching speed is difficult with a static control circuit. In the inventive technique, the AC switching behavior of a scaled-down buffer that is driven by a periodic signal generates the control voltage. In this manner, the factors that influence buffer switching speed, including process, voltage, and temperature variations, may be more accurately accounted for.

Abstract: A high-speed counter capable of counting the number of randomly incoming pulses is constructed by serially connecting a plurality of toggle flip-flop circuits, each of which is activated by input pulses and constructed from an rf-SQUID and the quantum flux parametron, whereby a high-speed computer or a high-speed measurement apparatus can be realised by the use of the high-speed counter.

Abstract: In a self-latching sense amplifier, a first pair of matched transistors is connected as a differential pair. A second pair of matched transistors is connected each to a respective one of the transistors of the first pair as a load transistor. A feedback circuit responsive to a differential output of the differential pair cross-couples the load transistors when the differential output is greater than a threshold value, and defeats cross-coupling of the load transistors when the differential output is less than the threshold value. The cross-coupling causes the output of the sense amplifier to latch. The sense amplifier is useful in memory circuits in which it is desired to shut down core components between memory operations to conserve power, and in other small signal detection circuits.

Abstract: In the preferred embodiment of the present invention flash write, a simultaneous and substantially identical write operation to a selected plurality of memory cells, is performed by splitting the pull up of the p sense amplifier transistors. The p sense amplifier transistor on digit is connected to V.sub.cc at its drain through a first pull up transistor and the p sense amplifier transistor on digit bar is connected to V.sub.cc at its drain through a second pull up transistor. A logic circuit generates control logic that actuates either both pull up transistors to initiate a typical read/write operation of a single memory cell or actuates one of the two pull up transistors to initiate a flash write to all of the memory cells on the selected wordline.