Abstract: A semiconductor device includes a current spreading region of the first conductivity type provided on a drift layer and having a higher impurity density than the drift layer; a base region of a second conductivity type provided on the current spreading region; a base contact region of the second conductivity type provided in a top part of the base region and having a higher impurity density than the base region; and an electrode contact region of the first conductivity type provided in a top part of the base region that is laterally in contact with the base contact region, the electrode contact region having a higher impurity density than the drift layer, wherein a density of a second conductivity type impurity element in the base contact region is at least two times as much as a density of a first conductivity type impurity element in the electrode contact region.

Abstract: A first electrode film is electrically connected to a source region of a semiconductor substrate, and disposed over a main surface of the semiconductor substrate. A second electrode film is electrically connected to a gate electrode, and disposed over the main surface. A third electrode film is disposed over the main surface away from the first electrode film. A protective dielectric film is disposed over the main surface, covers only a portion of each of the first electrode film and the second electrode film and covers at least portion of the third electrode film, and is made of a thermosetting resin. The main surface has a peripheral region and an inner region enclosed by the peripheral region, and the protective dielectric film has a peripheral portion covering the peripheral region and has a first inner portion crossing the inner region and covering at least portion of the third electrode film.

Abstract: A method includes etching a mandrel layer to form mandrel strips, and selectively depositing metal lines on sidewalls of the mandrel strips. During the selective deposition, top surfaces of the mandrel strips are masked by dielectric masks. The method further includes removing the mandrel layer and the dielectric masks, filling spaces between the metal lines with a dielectric material, forming via openings in the dielectric material, with top surfaces of the metal lines exposed to the via openings, and filling the via openings with a conductive material to form vias.

Abstract: An active array substrate includes a substrate and a plurality of pixel structure disposed on the substrate. Each of the pixel structure includes a scan line, a data line, and a pixel electrode. The scan line is disposed on the substrate and extending along a first direction. The data line is disposed on the substrate and extending along a second direction. The first direction crosses the second direction. The data line and the scan line define a pixel region and a first cutting clearance region. The pixel electrode is disposed on the substrate and includes a first portion and a second portion. The first portion is on the pixel region. The second portion is on the first cutting clearance region. A normal projection of the second portion onto the substrate does not overlap a normal projection of the data line onto the substrate.

Abstract: Described herein are the design and fabrication of Group III trioxides, such as ?-Ga2O3, trench-MOS barrier Schottky (TMBS) structures with high voltage (>1 kV), low leakage capabilities, while addressing on the necessary methods to meet the requirements unique to Group III trioxides, such as ?-Ga2O3.

Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.

Abstract: A semiconductor device is preferably excellent in characteristics such as a loss characteristic. Provided is a semiconductor device including a semiconductor substrate, including an upper-surface electrode provided on an upper surface of the semiconductor substrate; an lower-surface electrode provided on a lower surface of the semiconductor substrate; a transistor portion provided in the semiconductor substrate and connected to the upper-surface electrode and the lower-surface electrode; a first diode portion provided in the semiconductor substrate and connected to the upper-surface electrode and the lower-surface electrode; and a second diode portion provided in the semiconductor substrate and connected to the upper-surface electrode and the lower-surface electrode, wherein the first diode portion and the second diode portion have different resistivities in a depth direction of the semiconductor substrate.

Abstract: Embodiments of ferroelectric memory devices and methods for forming the ferroelectric memory devices are disclosed. In an example, a ferroelectric memory cell includes a first electrode, a second electrode, and a ferroelectric layer disposed between the first electrode and the second electrode. An edge region exposed by the first electrode and the second electrode is covered by at least one of a healing layer or a block layer.

Abstract: A semiconductor device includes a substrate, a plurality of circuit elements on a front side of the substrate, and a first substantially spiral-shaped conductor on a back side of the substrate is provided. The device further includes a first through-substrate via (TSV) electrically connecting a first end of the substantially spiral-shaped conductor to a first one of the plurality of circuit elements, and a second TSV electrically connecting a second end of the substantially spiral-shaped conductor to a second one of the plurality of circuit elements. The device may be a package further including a second die having a front side on which is disposed a second substantially spiral-shaped conductor. The front side of the second die is disposed facing the back side of the substrate, such that the first and second substantially spiral-shaped conductors are configured to wirelessly communicate.

Abstract: A pressure sensor device includes a semiconductor die having a die surface that includes a pressure sensitive area; and a bond wire bonded to a first peripheral region of the die surface and extends over the die surface to a second peripheral region of the die surface, wherein the pressure sensitive area is interposed between the second peripheral region and the first peripheral region, wherein the bond wire comprises a crossing portion that overlaps an area of the die surface, and wherein the crossing portion extends over the pressure sensitive area that is interposed between the first and the second peripheral regions.

Abstract: A method for forming a fin field effect transistor (FinFET) device structure and method for forming the same are provided. The method includes providing a substrate, and forming a fin structure on the substrate. The method also includes forming a protection layer on the sidewalls of the fin structure, and forming a dielectric layer on the fin structure and the protection layer. The method further includes removing a portion of the dielectric layer until a portion of the protection layer is exposed, and removing the exposed portion of the protection layer, such that the sidewalls of a lower portion of the fin structure are covered by the protection layer, and the sidewalls of an upper portion of the fin structure are not covered by the protection layer.

Abstract: A semiconductor device that is a chip-size-package-type semiconductor device that is facedown mountable includes: a semiconductor layer including a semiconductor substrate and a low-concentration impurity layer in contact with an upper surface of the semiconductor substrate; a metal layer having a thickness of at least 10 ?m; a first vertical MOS transistor in the semiconductor layer; and a second vertical MOS transistor in the semiconductor layer. A side surface of the metal layer includes roughness forming vertical stripes in a direction perpendicular to the metal layer, and has a maximum height of profile greater than 1.0 ?m. In a plan view of the semiconductor device, an area occupancy of a formation containing metal in the metal layer is at most 5% in a 10-?m square region located at least 13 ?m inward from an outer edge of the semiconductor device, within an upper surface of the semiconductor device.

Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.

Abstract: The disclosure is directed to spin-orbit torque (“SOT”) magnetoresistive random-access memory (“MRAM”) (“SOT-MRAM”) structures and methods. A SOT channel of the SOT-MRAM includes multiple heavy metal layers and one or more dielectric dusting layers each sandwiched between two adjacent heavy metal layers. The dielectric dusting layers each include discrete molecules or discrete molecule clusters of a dielectric material scattered in or adjacent to an interface between two adjacent heavy metal layers.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor member, first and second electrodes, a gate electrode, a gate terminal, a first conductive member, a first terminal, and a first insulating member. The semiconductor member includes first and second semiconductor regions, and a third semiconductor region provided between the first and second semiconductor regions. The first electrode is electrically connected to the first semiconductor region. The second electrode is electrically connected to the second semiconductor region. The gate terminal is electrically connected to the gate electrode. The first conductive member is electrically insulated from the first and second electrodes, and the gate electrode. The first terminal is electrically connected to the first conductive member.

Abstract: A semiconductor structure is provided. The semiconductor structure includes: a fin heat-dissipation region on a substrate; a fin channel part on the fin heat-dissipation region, and an isolation structure on the substrate. A width of the fin channel part is smaller than a width of the fin heat-dissipation region. A top surface of the isolation structure is coplanar with a top surface of the fin heat-dissipation region.

Abstract: An exemplary embodiment provides an organic light emitting diode display including a substrate, a bridge electrode disposed on the substrate, a buffer layer which covers the bridge electrode, a semiconductor layer disposed on the buffer layer, a first gate insulating layer which covers the semiconductor layer in a plan view, a first gate conductor disposed on the first gate insulating layer and which includes a first gate electrode, a second gate insulating layer which covers the first gate conductor, a second gate conductor disposed on the second gate insulating layer, an interlayer-insulating layer which covers the second gate conductor, and a data line disposed on the interlayer-insulating layer. The first gate electrode is directly connected to the bridge electrode, the semiconductor layer is electrically connected to the bridge electrode, and a capacitance exists between the data line and the bridge electrode.

Abstract: According to one embodiment, a resistive random access memory device includes a first electrode and a second electrode. The resistive random access memory device also includes a resistance change layer connected between the first electrode and the second electrode. The resistive random access memory device also includes a conductive layer connected in series to the resistance change layer between the first electrode and the second electrode. The resistive random access memory device in which the conductive layer includes a plurality of first material layers including a first material and a plurality of second material layers including a second material which is different from the first material.

Abstract: A semiconductor device includes first and second semiconductor fins, a first gate structure, and a second gate structure. The first and second semiconductor fins respectively includes a first channel region and a second channel region, which the first and second gate structures are respectively on. The first gate structure includes a first silicon oxide layer on the first channel region, a first high-k dielectric layer on the first silicon oxide layer, and a first metal gate on the first high-k dielectric layer. The second gate structure includes a second silicon oxide layer on the second channel region, a second high-k dielectric layer on the second silicon oxide layer, and a second metal gate on the second high-k dielectric layer. The first silicon oxide layer has a Si4+ ion concentration greater than a Si4+ ion concentration of a bottom portion of the second silicon oxide layer.

Abstract: A piezo-junction device may be provided. The piezo-junction device comprises a piezoelectric element comprising two electrodes and piezoelectric material in-between, and a semiconductor junction device adjacent to the piezoelectric element such that one of the two electrodes of the piezoelectric element is in contact with the semiconductor junction device connecting the semiconductor junction device and the piezoelectric element electrically in series. Thereby, the semiconductor junction device and the piezoelectric element are together positioned in a fixed mechanical clamp such that the piezoelectric element with an applied electrical field applies strain to the semiconductor junction device causing a change in Fermi levels of the semiconductor junction device.