Patents Examined by Jonas T Beardsley
  • Patent number: 10971544
    Abstract: Methods for forming a magneto-resistive memory device and a capacitor in an interconnect structure are disclosed herein. An exemplary method includes forming a first level interconnect metal layer and a second level interconnect metal layer of an interconnect structure. The method further includes simultaneously forming a first plurality of layers in a first region of the interconnect structure and a second plurality of layers in a second region of the interconnect structure, wherein the first plurality of layers and the second plurality of layers are disposed between the first level interconnect metal layer and the second level interconnect metal layer. The first plurality of layers is configured as a magneto-resistive memory device. The second plurality of layers is configured as the capacitor. The magneto-resistive memory device and the capacitor are each coupled to the first level interconnect metal layer and the second level interconnect metal layer.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Chung-Cheng Chou, Ya-Chen Kao, Tien-Wei Chiang
  • Patent number: 10937770
    Abstract: A light-emitting device having light-emitting elements with high operation stability and light extraction efficiency is provided. The light-emitting device includes: a substrate; light-emitting elements aligned and arranged on the substrate in an arrangement direction; wavelength conversion layers each disposed on each of the light-emitting elements with a light-transmitting adhesive interposed therebetween, each of the wavelength conversion layers having an upper surface smaller than a bottom surface, and a side surface shape in which a length in a lateral direction parallel to the bottom surface and perpendicular to the arrangement direction decreases from the bottom surface toward the upper surface; a light-transmitting plate disposed over the wavelength conversion layers; and a reflective resin covering side surfaces of the light-emitting elements, the wavelength conversion layers, and the light-transmitting plate.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: March 2, 2021
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventors: Mitsunori Harada, Kaori Tachibana, Satoshi Ando
  • Patent number: 10910498
    Abstract: An array substrate, a method for fabricating the same and a display device are disclosed. The method for fabricating the array substrate includes: forming a pattern of a gate electrode, a pattern of a gate insulation layer and a pattern of a metal oxide semiconductor active layer on a base substrate; forming an etch stop layer; forming a pattern of a pixel electrode first, and then forming a pattern of a source electrode and a pattern of a drain electrode; wherein the pattern of the pixel electrode is connected to the pattern of the metal oxide semiconductor active layer through the pattern of the source electrode or the pattern of the drain electrode. The method can prevent the problem that the pattern of the pixel electrode failing to connect to the pattern of the source electrode or the pattern of the drain electrode.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: February 2, 2021
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Zhanfeng Cao, Feng Zhang, Qi Yao
  • Patent number: 10886488
    Abstract: A display device is provided. The display device includes a first substrate, a first element layer, a first light-emitting element layer, a second substrate, a second element layer, and a second light-emitting element layer. The first element layer is disposed on the first substrate and includes a first active element. The first light-emitting element layer is disposed on the first element layer and includes a first light-emitting element, the first light-emitting element is electrically connected to the first active element and includes a first light-emitting layer. The second substrate is disposed on the first light-emitting element. The second element layer is disposed on the second substrate and includes a second active element. The second light-emitting element layer is disposed on the second element layer and includes a second light-emitting element, the second light-emitting element is electrically connected to the second active element and includes a second light-emitting layer.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: January 5, 2021
    Assignee: Au Optronics Corporation
    Inventors: Ya-Ting Hsu, Li-Chih Hsu, Chih-Ling Hsueh
  • Patent number: 10872843
    Abstract: A semiconductor device includes a substrate, a plurality of circuit elements on a front side of the substrate, and a first substantially spiral-shaped conductor on a back side of the substrate is provided. The device further includes a first through-substrate via (TSV) electrically connecting a first end of the substantially spiral-shaped conductor to a first one of the plurality of circuit elements, and a second TSV electrically connecting a second end of the substantially spiral-shaped conductor to a second one of the plurality of circuit elements. The device may be a package further including a second die having a front side on which is disposed a second substantially spiral-shaped conductor. The front side of the second die is disposed facing the back side of the substrate, such that the first and second substantially spiral-shaped conductors are configured to wirelessly communicate.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: December 22, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kyle K. Kirby
  • Patent number: 10861945
    Abstract: A semiconductor element includes a high-resistivity substrate that includes a ?-Ga2O3-based single crystal including an acceptor impurity, a buffer layer on the high-resistivity substrate, the buffer layer including a ?-Ga2O3-based single crystal, and a channel layer on the buffer layer, the channel layer including a ?-Ga2O3-based single crystal including a donor impurity. A crystalline laminate structure includes a high-resistivity substrate that includes a ?-Ga2O3-based single crystal including an acceptor impurity, a buffer layer on the high-resistivity substrate, the buffer layer including a ?-Ga2O3-based single crystal, and a donor impurity-containing layer on the buffer layer, the donor impurity-containing layer including a ?-Ga2O3-based single crystal including a donor impurity.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: December 8, 2020
    Assignees: TAMURA CORPORATION, NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY, NATIONAL UNIVERSITY CORPORATION TOKYO UNIVERSITY OF AGRICULTURE AND TECHNOLOGY
    Inventors: Kohei Sasaki, Ken Goto, Masataka Higashiwaki, Man Hoi Wong, Akinori Koukitu, Yoshinao Kumagai, Hisashi Murakami
  • Patent number: 10840369
    Abstract: A semiconductor device includes a current spreading region of the first conductivity type provided on a drift layer and having a higher impurity density than the drift layer; a base region of a second conductivity type provided on the current spreading region; a base contact region of the second conductivity type provided in a top part of the base region and having a higher impurity density than the base region; and an electrode contact region of the first conductivity type provided in a top part of the base region that is laterally in contact with the base contact region, the electrode contact region having a higher impurity density than the drift layer, wherein a density of a second conductivity type impurity element in the base contact region is at least two times as much as a density of a first conductivity type impurity element in the electrode contact region.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: November 17, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 10833187
    Abstract: A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. An n-type material is formed on or in the p-doped layer. The n-type material includes an oxide of a II-VI material. An oxygen scavenging interlayer is formed on the n-type material. An aluminum contact is formed in direct contact with the oxygen scavenging interlayer to form an electronic device.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeehwan Kim, Wencong Liu, Devendra K. Sadana
  • Patent number: 10804300
    Abstract: A complementary thin film transistor drive back-plate and manufacturing method thereof, a display panel.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: October 13, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Jang Soon Im
  • Patent number: 10797044
    Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate and a semiconductor fin located on the semiconductor substrate. The semiconductor fin includes a well region, a first doped region, and a second doped region. The first doped region and the second doped region are respectively adjacent to and being separated by a first portion of the well region. The device also includes a first gate structure on the semiconductor fin between the first doped region and the second doped region, and a first conductive structure electrically connecting the gate structure and the first doped region to a same potential. The ESD protection device can also have a third doped region and a second gate structure coupled to the same potential. The device also has a second conductive structure for connecting to a point between an external signal and a circuit to be protected.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: October 6, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Fei Zhou
  • Patent number: 10797030
    Abstract: Disclosed is a semiconductor package including a semiconductor chip, a first outer capacitor on the semiconductor chip including a first electrode and a second electrode, a second outer capacitor on the semiconductor chip including a first electrode pattern and a second electrode pattern, and a conductive pattern on the semiconductor chip and electrically connected to the first electrode of the first outer capacitor and the first electrode pattern of the second outer capacitor. The second electrode of the first outer capacitor is insulated from the second electrode pattern of the second outer capacitor.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: October 6, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangnam Jeong, IlJoon Kim, SunWon Kang
  • Patent number: 10790411
    Abstract: Embodiments of the present application relate to the use of quantum dots mixed with spacer particles. An illumination device includes a first conductive layer, a second conductive layer, and an active layer disposed between the first conductive layer and the second conductive layer. The active layer includes a plurality of quantum dots that emit light when an electric field is generated between the first and second conductive layers. The quantum dots are interspersed with spacer particles that do not emit light when the electric field is generated between the first and second conductive layers.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: September 29, 2020
    Assignee: Nanosys, Inc.
    Inventors: Jesse Manders, Christian Ippen, Donald Zehnder, Jonathan Truskier, Charles Hotz
  • Patent number: 10784255
    Abstract: A diode is provided having a plate-shaped semiconductor element that includes a first side and a second side, the first side being connected by a first connecting layer to a first metallic contact and the second side being connected by a second connecting layer to a second metallic contact, the first side having a diode element in a middle area and having a further diode element in an edge area of the first side, which has crystal defects as a result of a separating process of the plate-shaped semiconductor element, the first connecting layer only establishing an electrical contact to the diode element and not to the further diode element and, on the first side, the further diode element having an exposed contact, which may be electrically contacted by the first connecting layer.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: September 22, 2020
    Assignee: Robert Bosch GmbH
    Inventor: Alfred Goerlach
  • Patent number: 10763114
    Abstract: A method of fabricating a semiconductor device includes forming a semiconductor fin comprising a channel region for a fin field effect transistor (finFET). A gate oxide layer is then formed on the channel. The gate oxide layer is treated with a nitrogen containing agent so as to form a nitrogenous layer and an interfacial layer. The nitrogenous layer is then removed. A high-k dielectric layer is formed on the interfacial layer. A metal gate is formed on the high-k dielectric layer. The nitrogenous layer is removed by rinsing the semiconductor fin with deionized water. The gate oxide and interfacial layer contains the same material.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: September 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Andrew Joseph Kelly, Yusuke Oniki, Yasutoshi Okuno, Ta-Chun Ma
  • Patent number: 10696840
    Abstract: A resin composition for semiconductor encapsulation, containing (A) an epoxy resin, (B) a phenolic resin-based curing agent, (C) an inorganic filler, and (D) amorphous carbon, wherein the amorphous carbon of the component (D) contains 30 atomic % or more of an SP3 structure and 55 atomic % or less of an SP2 structure.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: June 30, 2020
    Assignee: KYOCERA CORPORATION
    Inventors: Ken Uchida, Shinichi Kazama, Yoshitake Terashi
  • Patent number: 10700170
    Abstract: Embodiments of the present invention provide a multiple fin field effect transistor (finFET) with low-resistance gate structure. A metallization line is formed in parallel with the gate, and multiple contacts are formed over the fins which connect the metallization line to the gate. The metallization line provides reduced gate resistance, which allows fewer transistors to be used for providing In-Out (IO) functionality, thereby providing space savings that enable an increase in circuit density.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: June 30, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Andy Chih-Hung Wei
  • Patent number: 10665760
    Abstract: A method for producing at least one optoelectronic semiconductor component and an optoelectronic semiconductor component are disclosed. In an embodiment, the method includes providing a semiconductor layer sequence comprising a first semiconductor material configured to emit a first radiation and applying a conversion element at least partially on the semiconductor layer sequence via a cold method, wherein the conversion element comprises a second semiconductor material, and wherein the second semiconductor material is configured to convert the first radiation into a second radiation.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: May 26, 2020
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Britta Goeoetz, Alexander Behres, Darshan Kundaliya
  • Patent number: 10651284
    Abstract: One illustrative method disclosed includes, among other things, selectively forming a gate-to-source/drain (GSD) contact opening and a CB gate contact opening in at least one layer of insulating material and forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure in their respective openings, wherein an upper surface of each of the GSD contact structure and the CB gate contact structure is positioned at a first level, and performing a recess etching process on the initial GSD contact structure and the initial CB gate contact structure to form a recessed GSD contact structure and a recessed CB gate contact structure, wherein a recessed upper surface of each of these recessed contact structures is positioned at a second level that is below the first level.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: May 12, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Youngtag Woo, Daniel Chanemougame, Bipul C. Paul, Lars W. Liebmann, Heimanu Niebojewski, Xuelian Zhu, Lei Sun, Hui Zang
  • Patent number: 10629808
    Abstract: A method for forming a phase change random access memory is provided. The method includes providing a substrate having a surface; and forming a dielectric layer on the surface of the substrate. The method also includes forming a through-hole penetrating through the dielectric layer; and forming an adhesion layer on inner surface of the through-hole. Further, the method includes forming a metal layer doped with inorganic ions on the adhesion layer to reduce over-etching of the metal layer and increase heating efficiency of the metal layer on the surface of the adhesion layer; and forming a phase change layer on the dielectric layer, the adhesion layer and the doped metal layer.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: April 21, 2020
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Zhichao Li, Guangcai Fu
  • Patent number: 10615162
    Abstract: The semiconductor device includes a first fin-type pattern and a second fin-type pattern which extends along a first direction; a first gate structure and a second gate structure extending in a second direction, on the first fin-type pattern and the second fin-type pattern; and a shared epitaxial pattern which connects the first fin-type pattern and the second fin-type pattern between the first gate structure and the second gate structure. An upper surface of the shared epitaxial pattern includes a first shared slope and a second shared slope which connect the first gate structure and the second gate structure, a third shared slope which is in contact with the first gate structure and connects the first shared slope and the second shared slope, and a fourth shared slope which is in contact with the second gate structure and connects the first shared slope and the second shared slope.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: April 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun Kwan Yu, Won Hyung Kang, Hyo Jin Kim, Sung Bu Min