Abstract: The present disclosure provides a semiconductor device that includes a substrate, a first fin structure over the substrate. The first fin structure includes a first semiconductor material layer, having a semiconductor oxide layer as its outer layer, as a lower portion of the first fin structure. The first semiconductor has a first width. The first fin structure also includes a second semiconductor material layer as an upper portion of the first fin structure. The second semiconductor material layer has a third width, which is substantially smaller than the first width. The semiconductor structure also includes a gate region formed over a portion of the first fin and a high-k (HK)/metal gate (MG) stack on the substrate including wrapping over a portion of the first fin structure in the gate region.

Abstract: A novel oxide semiconductor, a novel oxynitride semiconductor, a transistor including them, or a novel sputtering target is provided. A composite target includes a first region and a second region. The first region includes an insulating material and the second region includes a conductive material. The first region and the second region each include a microcrystal whose diameter is greater than or equal to 0.5 nm and less than or equal to 3 nm or a value in the neighborhood thereof. A semiconductor film is formed using the composite target.

Abstract: A silicon carbide semiconductor device includes: an element isolation layer and an electric field relaxation layer. The element isolation layer is arranged, from the surface of a base region to be deeper than the base region, between a main cell region and a sense cell region, and isolates the main cell region from the sense cell region. The electric field relaxation layer is arranged from a bottom of the base region to be deeper than the element isolation layer. The electric field relaxation layer is divided into a main cell region portion and a sense cell region portion. At least a part of the element isolation layer is arranged inside of a division portion of the electric field relaxation layer.

Abstract: A method of fabricating a semiconductor structure includes providing an engineered substrate including a polycrystalline substrate, a barrier layer encapsulating the polycrystalline substrate, and a bonding layer coupled to the barrier layer. The method further includes forming a first silicon layer coupled to the bonding layer, forming a dielectric layer coupled to the first silicon layer, forming a second silicon layer coupled to the dielectric layer, removing a portion of the second silicon layer and a corresponding portion of the dielectric layer to expose a portion of the first silicon layer, forming a gallium nitride (GaN) layer coupled to the exposed portion of the first silicon layer, forming a gallium nitride (GaN) based device coupled to the GaN layer, and forming a silicon-based device coupled to a remaining portion of the second silicon layer.

Abstract: Semiconductor devices may include a substrate and a semiconductor die on the substrate. The semiconductor die may include an active surface and a lateral edge at a periphery of the active surface. An electrically insulating material may be located on the active surface proximate the lateral edge. The electrically insulating material may be distinct from any other material located on the active surface. A wire bond may extend from the active surface, over the electrically insulating material, to the substrate. Methods of making semiconductor devices may involve positioning an electrically insulating material on an active surface of a semiconductor die proximate a lateral edge at a periphery of an active surface. After positioning the electrically insulating material on the active surface, a wire bond extending from the active surface, over the electrically insulating material, to the substrate may be formed.

Abstract: An array substrate, a method for fabricating the same and a display device are disclosed. The array substrate includes: a gate electrode of a TFT and a gate insulation layer sequentially formed on a base substrate; a semiconductor active layer, an etch stop layer and a source electrode and a drain electrode of the TFT sequentially formed on a part of the gate insulation layer that corresponds to the gate electrode of the TFT, the source and drain electrodes of the TFT are respectively in contact with the semiconductor active layer by way of via holes. The array substrate further includes: a first insulation layer formed between the gate electrode of the TFT and the gate insulation layer and the gate electrode is in contact with the gate insulation layer at a channel region of the TFT between the source electrode and the drain electrode of the TFT.

Abstract: A semiconductor device comprises a semiconductor substrate, a silicon carbide semiconductor layer of a first conductivity type on the semiconductor substrate, at least one ring-shaped region of a second conductivity type in the silicon carbide semiconductor layer, a first insulating film in contact with a part of the silicon carbide semiconductor layer, and a second insulating film which has a relative dielectric constant larger than a relative dielectric constant of the first insulating film and which is in contact with a part of the at least one ring-shaped region. In the semiconductor device, the at least one ring-shaped region is located in a termination region. The termination region surrounds a semiconductor element region when viewed from the direction perpendicular to a principal surface of the semiconductor substrate.

Abstract: Provided is a semiconductor device including a gate structure, a first doped region of a first conductivity type, a plurality of second doped regions of a second conductivity type, a third doped region of the first conductivity type, and a plurality of fourth doped regions of the second conductivity type. The gate structure is located on a substrate. The first doped region is located in the substrate on a first side of the gate structure. The second doped regions are located in the first doped region. The second doped regions are separated from each other. The third doped region is located in the substrate on a second side of the gate structure. The fourth doped regions are located in the third doped region. The fourth doped regions are separated from each other. The second doped regions and the fourth doped regions are disposed alternately.

Abstract: A semiconductor device includes: a semiconductor substrate having a main plane; a semiconductor element provided on the main plane of the semiconductor substrate; an electrode pad provided on the main plane of the semiconductor substrate and connected to the semiconductor element; a guard ring surrounding the semiconductor element and the electrode pad, and provided on the main plane of the semiconductor substrate; and an insulating film covering all region of a semiconductor of the main plane of the semiconductor substrate exposed inside the guard ring, wherein the insulating film is made of a water impermeable material.

Abstract: A first architecture for a volatile resistive-switching device with a selector layer (e.g., a highly resistive layer such as a resistive switching medium) non-planar surfaces is detailed. For example, the selector layer can have a first surface that intersects a second surface at an angle (e.g., oblique angle). The angle can be adjusted to control current-voltage response for the volatile resistive-switching device. A second architecture for volatile resistive-switching device with a first terminal having a high particle diffusivity and a second terminal having a low particle diffusivity. The second architecture can provide diode-like current-voltage responses at a sizes (e.g., sub-20 nanometers) in which conventional diodes do not scale.

Abstract: The present invention discloses a composite gate dielectric layer for a Group III-V substrate and a method for manufacturing the same. The composite gate dielectric layer comprises: an AlxY2-xO3 interface passivation layer formed on the group III-V substrate; and a high dielectric insulating layer formed on the AlxY2-xO3 interface passivation layer, wherein 1.2?x?1.9. The composite gate dielectric layer modifies the Al/Y ratio of the AlxY2-xO3 interface passivation layer, changes the average number of atomic coordination in the AlxY2-xO3 interface passivation layer, and decreases the interface state density and boundary trap density of the Group III-V substrate, increases the mobility of the MOS channel. By cooperation of the AlxY2-xO3 interface passivation layer and high dielectric insulation layer, it reduces leakage current and improves tolerance of the dielectric layer on the voltage, and improves the quality of the MOS capacitor of the Group III-V substrate and enhances its reliability.

Abstract: A semiconductor device includes: a semiconductor substrate having a main plane; a semiconductor element provided on the main plane of the semiconductor substrate; an electrode pad provided on the main plane of the semiconductor substrate and connected to the semiconductor element; a guard ring surrounding the semiconductor element and the electrode pad, and provided on the main plane of the semiconductor substrate; and an insulating film covering all region of a semiconductor of the main plane of the semiconductor substrate exposed inside the guard ring, wherein the insulating film is made of a water impermeable material.

Abstract: An LED light emitting device with good color mixing property is provided. The LED light emitting device including a rectangular substrate having a short-side and a long-side and a first LED element, a second LED element and a third LED element that are mounted on a surface of the substrate and emit light with wavelengths different from one another, wherein the first LED element and the second LED element are mounted on the substrate so that a first distance from the short-side to a mounting position of the first LED element in the long-side direction of the substrate and a second distance from the short-side to a mounting position of the second LED element in the long-side direction are the same.

Abstract: A method for manufacturing a semiconductor device comprises forming a plurality of silicon fins on a substrate, wherein the plurality of silicon fins are spaced apart from each other at a pitch and formed to a height in a direction perpendicular to a top surface of the substrate, forming a nitride layer between each of adjacent silicon fins and on lateral surfaces of each of the silicon fins, removing a portion of each of the silicon fins to reduce the height of the silicon fins, epitaxially growing a silicon germanium (SiGe) layer on the remaining portion of each of the silicon fins, performing a top-down condensation process on the epitaxially grown SiGe layers to form an oxide layer and an SiGe fin under the oxide layer in place of each epitaxially grown SiGe layer and the remaining portion of each silicon fin, and removing the oxide layers and nitride layers.

Abstract: A light emitting device includes: a substrate; an electrode pattern formed on the substrate; a light emitting element connected to the electrode pattern; a ridge-shaped resin covering portion which covers a part of the electrode pattern, and which includes a first and second outer edge portions; first and second through holes formed to penetrate through the electrode pattern such that the substrate is exposed; and first and second hole arrays including the first and second through holes arranged along the first and second outer edge portions, respectively. The first and second outer edge portions cover at least a part of the first and second through holes, respectively, and are bonded to the substrate in the first and second through holes, respectively.

Abstract: A method of making a vertical field effect transistor includes forming a semiconductor nanowire that extends from a substrate surface. A first sacrificial layer is deposited over the substrate surface, and a second sacrificial layer is deposited over the first sacrificial layer such that each of the first and second sacrificial layers are formed peripheral to the nanowire. The second sacrificial layer is then patterned to form a dummy gate structure. Thereafter, the first sacrificial layer is removed and source and drain regions are deposited via epitaxy directly over respective portions of the nanowire.

Abstract: A finned structure is fabricated using a bulk silicon substrate having a carbon-doped epitaxial silicon germanium layer. A pFET region of the structure includes fins having silicon germanium top portions and an epitaxial carbon-doped silicon germanium diffusion barrier that suppresses dopant diffusion from the underlying n-well into the silicon germanium fin region during device fabrication. The structure further includes an nFET region including silicon fins formed from the substrate. The carbon-doped silicon germanium diffusion barrier has the same or higher germanium content than the silicon germanium fins.

Abstract: Methods and devices are provided to fabricate semiconductor devices with, e.g., SiGe-on-insulator structures. For example, a method for fabricating a semiconductor device includes forming a crystalline buffer layer on a substrate, forming an epitaxial semiconductor layer on the crystalline buffer layer, patterning the epitaxial semiconductor layer to form a patterned epitaxial semiconductor layer, and oxidizing a surface region of the crystalline buffer layer selective to the patterned epitaxial semiconductor layer to convert the surface region of the crystalline buffer layer to an insulating layer. The insulating layer insulates the patterned epitaxial semiconductor layer from the crystalline buffer layer. In one example structure, the substrate is a silicon substrate, the crystalline buffer layer is formed of germanium, the epitaxial semiconductor layer is formed of silicon-germanium, and the insulating layer is formed of amorphous germanium-oxide.

Abstract: A gate structure is formed across a single crystalline semiconductor fin. An amorphizing ion implantation is performed employing the gate structure as an implantation mask to amorphize surface portions of the semiconductor fin into inverted U-shaped amorphous semiconductor portions. A gate spacer is formed around the gate structure, and the inverted U-shaped amorphous semiconductor portions are etched selective to a single crystalline portion of the semiconductor fin and the gate structure. A pair of inverted U-shaped cavities is formed underneath the gate spacer and above the remaining portion of the semiconductor fin. A doped epitaxial semiconductor material is deposited by a selective epitaxy process to form doped epitaxial active regions that include self-aligned extension portions underlying the gate spacer.

Abstract: A semiconductor device includes: a semiconductor substrate having a main plane; a semiconductor element provided on the main plane of the semiconductor substrate; an electrode pad provided on the main plane of the semiconductor substrate and connected to the semiconductor element; a guard ring surrounding the semiconductor element and the electrode pad, and provided on the main plane of the semiconductor substrate; and an insulating film covering all region of a semiconductor of the main plane of the semiconductor substrate exposed inside the guard ring, wherein the insulating film is made of a water impermeable material.