Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes forming an isolation layer on a substrate. The isolation layer includes an opening, and a bottom of the opening exposes the substrate. The method also includes forming a fin in the opening. The fin includes a heat-dissipation region and a channel region on the heat-dissipation region. Moreover, the fin includes forming an isolation structure by removing a thickness portion of the isolation layer. A surface of the isolation structure is coplanar with a surface of the heat-dissipation region of the fin. Further, the method includes forming a channel part from the channel region by performing a thinning process to reduce a width of the channel region of the fin using the isolation structure as a mask. The heat-dissipation region of the fin forms a heat-dissipation part.

Abstract: A semiconductor device according to the present invention includes a semiconductor layer, a gate trench defined in the semiconductor layer, a first insulating film arranged on the inner surface of the gate trench, a gate electrode arranged in the gate trench via the first insulating film, and a source layer, a body layer, and a drain layer arranged laterally to the gate trench, in which the first insulating film includes, at least at the bottom of the gate trench, a first portion and a second portion with a film elaborateness lower than that of the first portion from the inner surface of the gate trench in the film thickness direction.

Abstract: Methods are disclosed herein for forming fin-like field effect transistors (FinFETs) that maximize strain in channel regions of the FinFETs. An exemplary method includes forming a fin having a first width over a substrate. The fin includes a first semiconductor material, a second semiconductor material disposed over the first semiconductor material, and a third semiconductor material disposed over the second semiconductor material. A portion of the second semiconductor material is oxidized, thereby forming a second semiconductor oxide material. The third semiconductor material is trimmed to reduce a width of the third semiconductor material from the first width to a second width. The method further includes forming an isolation feature adjacent to the fin. The method further includes forming a gate structure over a portion of the fin, such that the gate structure is disposed between source/drain regions of the fin.

Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.

Abstract: The disclosure is directed to spin-orbit torque (“SOT”) magnetoresistive random-access memory (“MRAM”) (“SOT-MRAM”) structures and methods. A SOT channel of the SOT-MRAM includes multiple heavy metal layers and one or more dielectric dusting layers each sandwiched between two adjacent heavy metal layers. The dielectric dusting layers each include discrete molecules or discrete molecule clusters of a dielectric material scattered in or adjacent to an interface between two adjacent heavy metal layers.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a shallow trench isolation (STI) region on a well region of a substrate, a plurality of transistors, and a power rail. Each of the transistors includes at least one fin, a gate electrode formed on the fin, and a doping region formed on the fin. The fin is formed on the well region, and is extending in a first direction. The gate electrode is extending in a second direction that is perpendicular to the first direction. The power rail is formed in the STI region and below the doping regions of the transistors, and extending in the first direction. Each of the doping regions is electrically connected to the power rail, so as to form a source region of the respective transistor. The power rail is electrically connected to the well region of the substrate.

Abstract: An electronic device including a two-dimensional electron gas is provided. The electronic device includes a substrate, a first material layer disposed on the substrate and formed of a binary oxide, a second material layer disposed on the first material layer and formed of a binary oxide, and a two-dimensional electron gas generated between the first material layer and the second material layer.

Abstract: A pressure sensor device includes a semiconductor die of the pressure sensor device and a bond wire of the pressure sensor device. A maximal vertical distance between a part of the bond wire and the semiconductor die is larger than a minimal vertical distance between the semiconductor die and a surface of a gel covering the semiconductor die.

Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.

Abstract: Disclosed is a semiconductor package including a semiconductor chip, a first outer capacitor on the semiconductor chip including a first electrode and a second electrode, a second outer capacitor on the semiconductor chip including a first electrode pattern and a second electrode pattern, and a conductive pattern on the semiconductor chip and electrically connected to the first electrode of the first outer capacitor and the first electrode pattern of the second outer capacitor. The second electrode of the first outer capacitor is insulated from the second electrode pattern of the second outer capacitor.

Abstract: Methods for forming a magneto-resistive memory device and a capacitor in an interconnect structure are disclosed herein. An exemplary method includes forming a first level interconnect metal layer and a second level interconnect metal layer of an interconnect structure. The method further includes simultaneously forming a first plurality of layers in a first region of the interconnect structure and a second plurality of layers in a second region of the interconnect structure, wherein the first plurality of layers and the second plurality of layers are disposed between the first level interconnect metal layer and the second level interconnect metal layer. The first plurality of layers is configured as a magneto-resistive memory device. The second plurality of layers is configured as the capacitor. The magneto-resistive memory device and the capacitor are each coupled to the first level interconnect metal layer and the second level interconnect metal layer.

Abstract: A light-emitting device having light-emitting elements with high operation stability and light extraction efficiency is provided. The light-emitting device includes: a substrate; light-emitting elements aligned and arranged on the substrate in an arrangement direction; wavelength conversion layers each disposed on each of the light-emitting elements with a light-transmitting adhesive interposed therebetween, each of the wavelength conversion layers having an upper surface smaller than a bottom surface, and a side surface shape in which a length in a lateral direction parallel to the bottom surface and perpendicular to the arrangement direction decreases from the bottom surface toward the upper surface; a light-transmitting plate disposed over the wavelength conversion layers; and a reflective resin covering side surfaces of the light-emitting elements, the wavelength conversion layers, and the light-transmitting plate.

Abstract: An array substrate, a method for fabricating the same and a display device are disclosed. The method for fabricating the array substrate includes: forming a pattern of a gate electrode, a pattern of a gate insulation layer and a pattern of a metal oxide semiconductor active layer on a base substrate; forming an etch stop layer; forming a pattern of a pixel electrode first, and then forming a pattern of a source electrode and a pattern of a drain electrode; wherein the pattern of the pixel electrode is connected to the pattern of the metal oxide semiconductor active layer through the pattern of the source electrode or the pattern of the drain electrode. The method can prevent the problem that the pattern of the pixel electrode failing to connect to the pattern of the source electrode or the pattern of the drain electrode.

Abstract: A display device is provided. The display device includes a first substrate, a first element layer, a first light-emitting element layer, a second substrate, a second element layer, and a second light-emitting element layer. The first element layer is disposed on the first substrate and includes a first active element. The first light-emitting element layer is disposed on the first element layer and includes a first light-emitting element, the first light-emitting element is electrically connected to the first active element and includes a first light-emitting layer. The second substrate is disposed on the first light-emitting element. The second element layer is disposed on the second substrate and includes a second active element. The second light-emitting element layer is disposed on the second element layer and includes a second light-emitting element, the second light-emitting element is electrically connected to the second active element and includes a second light-emitting layer.

Abstract: A semiconductor device includes a substrate, a plurality of circuit elements on a front side of the substrate, and a first substantially spiral-shaped conductor on a back side of the substrate is provided. The device further includes a first through-substrate via (TSV) electrically connecting a first end of the substantially spiral-shaped conductor to a first one of the plurality of circuit elements, and a second TSV electrically connecting a second end of the substantially spiral-shaped conductor to a second one of the plurality of circuit elements. The device may be a package further including a second die having a front side on which is disposed a second substantially spiral-shaped conductor. The front side of the second die is disposed facing the back side of the substrate, such that the first and second substantially spiral-shaped conductors are configured to wirelessly communicate.

Abstract: A semiconductor element includes a high-resistivity substrate that includes a ?-Ga2O3-based single crystal including an acceptor impurity, a buffer layer on the high-resistivity substrate, the buffer layer including a ?-Ga2O3-based single crystal, and a channel layer on the buffer layer, the channel layer including a ?-Ga2O3-based single crystal including a donor impurity. A crystalline laminate structure includes a high-resistivity substrate that includes a ?-Ga2O3-based single crystal including an acceptor impurity, a buffer layer on the high-resistivity substrate, the buffer layer including a ?-Ga2O3-based single crystal, and a donor impurity-containing layer on the buffer layer, the donor impurity-containing layer including a ?-Ga2O3-based single crystal including a donor impurity.

Abstract: A semiconductor device includes a current spreading region of the first conductivity type provided on a drift layer and having a higher impurity density than the drift layer; a base region of a second conductivity type provided on the current spreading region; a base contact region of the second conductivity type provided in a top part of the base region and having a higher impurity density than the base region; and an electrode contact region of the first conductivity type provided in a top part of the base region that is laterally in contact with the base contact region, the electrode contact region having a higher impurity density than the drift layer, wherein a density of a second conductivity type impurity element in the base contact region is at least two times as much as a density of a first conductivity type impurity element in the electrode contact region.

Abstract: A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. An n-type material is formed on or in the p-doped layer. The n-type material includes an oxide of a II-VI material. An oxygen scavenging interlayer is formed on the n-type material. An aluminum contact is formed in direct contact with the oxygen scavenging interlayer to form an electronic device.

Abstract: A complementary thin film transistor drive back-plate and manufacturing method thereof, a display panel.

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate and a semiconductor fin located on the semiconductor substrate. The semiconductor fin includes a well region, a first doped region, and a second doped region. The first doped region and the second doped region are respectively adjacent to and being separated by a first portion of the well region. The device also includes a first gate structure on the semiconductor fin between the first doped region and the second doped region, and a first conductive structure electrically connecting the gate structure and the first doped region to a same potential. The ESD protection device can also have a third doped region and a second gate structure coupled to the same potential. The device also has a second conductive structure for connecting to a point between an external signal and a circuit to be protected.